參數(shù)資料
型號： GCIXP1250-232
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 15/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-232
Intel
IXP1250 Network Processor
Datasheet
15
two devices are not reset synchronously, bus contention could result if one of the devices is held in
reset while the alternate device assumes the role of initial IX Bus owner and begins driving
transactions. This would result in obvious bus malfunction, and over time could affect device
reliability due to resulting high current conditions in the device.
2.5
SDRAM and SRAM Units
The IXP1250 supports two high performance memory units. The SRAM Unit provides fast
memory that can be used to store look-up tables. The SDRAM Unit provides lower cost memory
for forwarding information and transmit queues. Both units contain features that improve memory
bandwidth utilization.
2.5.1
SDRAM Unit
The IXP1250 provides an SDRAM Unit to access low cost, high bandwidth memory for mass data
storage. The StrongARM* core address space allows up to 256 Mbytes of SDRAM to be
addressed. The SDRAM interface operates at half the Core frequency (0.5*F
core
), providing a peak
bandwidth of 800 Mbytes per second at 232 MHz.
Bus cycles are generated by requests from the PCI Unit including PCI DMA cycles, the
StrongARM* core, and the Microengines.
The SDRAM is operated by commands that are loaded into command queues within the unit. The
SDRAM Unit decodes the command, reads or writes the data, then deletes the command from the
head of the queue. The read and write sources may be SDRAM memory locations, transfer
registers, or the Transmit and Receive FIFOs in the FBI Unit. Refer to the
IXP1200 Network
Processor Family Hardware Reference Manual
for details on how these requests are queued,
prioritized, and serviced by the SDRAM Unit.
SDRAM should have an access time (t
ac
) of 6 ns or less (CAS latency = 2), PC100 compatible.
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