參數(shù)資料
型號： GCIXP1250-232
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 20/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-232
Intel
IXP1250 Network Processor
20
Datasheet
SRAM_SLOWPORT_CONFIG register fields. See
Figure 73
which illustrates this example. The
SCC value is the total number of Core clocks for the I/O cycle, and the SRWA, SCEA, SRWD, and
SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O
cycles begins, the SCC value is loaded into the internal state counter and is decremented on each
Core clock tick (twice the SCLK frequency). When the state counter reaches the RDY_L Pause
State Value, it will remain in that state until the HIGH_EN_L pin is sampled LOW, allowing the
state counter to resume its decrement operation. The HIGH_EN_L must be driven for at least two
SCLK periods to be sampled properly by the IXP1250.
The RDY_L Pause State must also occur at a minimum of 5 Core clock periods prior to the SRWD
state to be recognized. A RDY_L Pause State value of SRWD+5 (Decimal 10, Hexidecimal A) is
used in this example.
In this example, 6 additional Core clock
“
wait-states
”
are inserted. If the RDY_L input is
synchronous to SCLK and it meets the specified setup and hold times, the resulting number of wait
states will be predictable. However, if the RDY_L input is asynchronous to SCLK, the number of
wait-states the IXP1250 inserts could vary by +/- 2 Core clock periods.
2.5.6.1
SRAM Types Supported
Pipeline Burst DCD (double cycle deselect) type: tKQmax=4.2 ns, 3.3 V.
Flowthru type: tKQmax= 9 ns, 3.3 V.
Note:
Other SSRAM devices, including single cycle deselect, are not supported.
2.5.6.2
SRAM Configurations
Table 7. SRAM Configurations
Total Memory
Number of Chips
(Maximum of 8)
Size of SRAM
Device Organization
1 Mbytes
8
1 Mbit
32 K x 32-bit
2 Mbytes
8
2 Mbit
64 K x 32-bit
2 Mbytes
8
2 Mbit
128 K x 16-bit
4 Mbytes
8
4 Mbit
128 K x 32-bit
4 Mbytes
8
4 Mbit
256 K x 16-bit
8 Mbytes (maximum)
8
8 Mbit
256 K x 32-bit
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