參數(shù)資料
型號： GCIXP1250-232
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 38/148頁
文件大小： 1601K
代理商： GCIXP1250-232
Intel
IXP1250 Network Processor
38
Datasheet
3.3.7
PCI Interface Pins
Table 18. PCI Interface Pins
PCI Interface
Signal Names
Pin
Number
Type
Total
Pin Descriptions
AD[31:0]
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
D19
C19
B19
D18
C18
B18
A18
E17
B17
A17
B15
C15
D15
E15
A14
B14
C12
D12
E12
B11
C11
D11
A10
C10
A9
E10
B9
C9
D9
A8
E9
B8
I2/O2/
TS
32
Address/data. These signals are multiplexed address and
data bus. The IXP1250 receives addresses as target and
drives addresses as master. It receives write data and drives
read data as target. It drives write data and receives read
data as master.
CBE_L[3:0]
[3]
[2]
[1]
[0]
D17
C14
B12
D10
I2/O2/
TS
4
Command byte enables. These signals are multiplexed
command and byte enable signals. The IXP1250 receives
commands as target and drives commands as master. It
receives byte enables as target and drives byte enables as
master.
PAR
A12
I2/O2/
TS
1
Parity. This signal carries even parity for AD and CBE_L
pins. It has the same receive and drive characteristics as the
address and data bus, except that it occurs on the next PCI
clock cycle.
FRAME_L
D14
I2/O2/
STS
1
FRAME_L indicates the beginning and duration of an
access. The IXP1250 receives as target and drives as
master.
IRDY_L
E14
I2/O2/
STS
1
Initiator ready. Indicates the master
’
s ability to complete the
current data phase of the transaction. The IXP1250 receives
as target and drives as master.
TRDY_L
A13
I2/O2/
STS
1
Target ready. Indicates the target
’
s ability to complete the
current data phase of the transaction. The IXP1250 drives as
target and receives as master.
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