參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 33/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
Datasheet
33
3.3.4
IX Bus Interface Pins
Table 15. IX Bus Interface Pins
IX Bus Signal
Names
Pin
Number
Type
Total
Pin Descriptions
FCLK
AB30
I3
1
IX Bus Clock input. All IX Bus transfers are synchronized to
this clock. Typical operating frequency 33 MHz - 104 MHz.
PORTCTL_L[3:0]
[3]
[2]
[1]
[0]
AC30
AB27
AC31
AB28
O1/TS
4
Port Control outputs. Used to select the transmit and/or
receive mode for IX Bus devices, typically MAC devices.
In 64-bit bidirectional IX Bus mode, this is a 4-bit bus used to
indicate transmit or receive commands and device selects.
In 32-bit unidirectional IX Bus mode, bits [1:0] are used to
select the receive device and bits [3:2] are used to select the
transmit device.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
FPS[2:0]
[2]
[1]
[0]
AC29
AC28
AD31
O4/TS 3
MAC Port Select outputs.
In 32-bit and 64-bit modes, these pins select one of eight
MAC receive ports from the selected MAC device. See IX
Bus control signal decode tables.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
FDAT[63:0]
[63]
[62]
[61]
[60]
[59]
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
[50]
[49]
[48]
[47]
[46]
[45]
[44]
[43]
[42]
[41]
[40]
[39]
[38]
[37]
[36]
[35]
[34]
[33]
[32]
[31]
AC27
AD30
AD29
AD28
AE30
AE29
AE28
AF30
AE27
AF29
AG31
AF28
AG30
AJ26
AG25
AK26
AH25
AJ25
AK25
AG24
AL25
AH24
AJ24
AK24
AG23
AL24
AH23
AJ23
AK23
AG22
AL23
AH22
AJ22
I2/O5/
TS
64
IX Bus Data.
One 64-bit bus in bidirectional IX Bus mode.
Two 32-bit buses in unidirectional IX Bus mode where bits
[63:32] are used for Transmit Data output and [31:0] are
used for Receive Data input.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
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