參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 16/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
16
Datasheet
Figure 3
details the major components of the SDRAM Unit.
The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS_L, CAS_L, write
enable, DQM control, and a synchronous output clock running at one-half the IXP1250 Core
frequency (0.5*F
core
).
The PCI, Microengines, and StrongARM* core require single byte, word, and longword write
capabilities. The SDRAM Unit supports this using a read-modify-write technique. As data is
written from the PCI or StrongARM* core to SDRAM, a quadword is read from SDRAM. The
IXP1250 then updates only the bytes that were enabled and writes the entire quadword of data back
to SDRAM memory. (Note that the bytes do not have to be consecutive.) These three steps are
performed automatically.
2.5.2
SDRAM Bus Access Behavior
The number of quadwords transferred by the SDRAM Unit is determined by the requesting
interface (StrongARM* core, Microengine, or PCI). The SDRAM Unit may reorder SDRAM
accesses for best performance.
Accesses are always quadword (64-bit) cycles on the SDRAM Bus.
Accesses from the StrongARM* core.
—
Byte, word, and longword accesses generated from the StrongARM* core result in
Read-Modify-Write cycles to SDRAM space.
—
Consecutive longword writes over the AMBA Bus to the same quadword address are
buffered and aggregated into quadword writes to SDRAM.
Figure 3. SDRAM Unit Block Diagram
A8544-01
AMBA[31:0]
(from
StrongARM
*
Core)
Microengine
Commands &
Addresses
Microengine Data [63:0]
SDRAM
up to
256 MB
SDRAM
Pin
Interface
Command
Decoder
& Address
Generator
Service Priority
(Arbitration)
Machine & Registers
AMBA Bus
Interface
Logic
AMBA Address
Rd/Wr Queue
PCI Address
RD/Wr Queue
Microengine Address
& Command Queues
(High Priority, Even,
Odd & Order)
Memory/
AMBA Data
FIFO
Addr[14:0]
Data[63:0]
WE_L,RAS_L
CAS_L, DQM
addr
data
SDCLK
PCI Commands
and Addresses
* Other names and brands may be claimed as the property of others.
** ARM architecture compatible
MDATA_ECC[7:0]
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