參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 13/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
Datasheet
13
In addition, a shared IX Bus mode is supported in 64-bit bidirectional mode. Refer to the list at the
bottom of
Table 26
for the signals that the IX Bus masters must drive and IX Bus slaves must
tri-state.
The IX Bus and Intel devices using the IX Bus, such as the IXF440 and IXF1002, observe a
pipelined bus protocol. When receive transfers are terminated early, the pipeline continues to cause
several extra bus cycles depending on when the EOP signal was asserted. Data is a
“
don't care
”
for
these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a
possible status transfer if the device were programmed to support it. Slave devices must drive valid
logic levels on the FDAT data pins during these cycles.
The tables below show the number of total IX Bus data cycles that will occur for a burst with EOP
asserted at specific clocks for 64-bit and 32-bit IX Bus modes. In each case, the tables show IX Bus
cycles with and without the optional status transfer cycle. Refer to the IX Bus Protocol Timing
diagrams (
Figure 21
through
Figure 54
) when interpreting these tables.
Table 1. 64-bit IX Bus Receive Remainder Cycles, No Status Transfer
EOP signaled on this
cycle:
1
2
3
4
5
6
7
8
Number of bus cycles in
burst:
5
6
7
8
8
8
8
8
Number of Don
’
t Care
cycles:
4
4
4
4
3
2
1
0
Table 2. 64-bit IX Bus Receive Remainder Cycles, with Status Transfer
EOP signaled on this
cycle:
1
2
3
4
5
6
7
8
Number of bus cycles in
burst:
5
6
7
8
8
8
8
8
Status transfer
1
1
1
1
1
1
1
Note 1
Number of Don
’
t Care
cycles:
3
3
3
3
2
1
0
0
NOTE:
1. Status transfer occurs on a subsequent IX Bus status cycle.
Table 3. 32-bit IX Bus Receive Remainder Cycles, No Status Transfer
EOP signaled on this
cycle:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Number of bus cycles in
burst:
5
6
7
8
9
10
11
12
13
14
15
16
16
16
16
16
Number of Don
’
t Care
cycles:
4
4
4
4
4
4
4
4
4
4
4
4
3
2
1
0
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