參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 39/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
Datasheet
39
STOP_L
C13
I2/O2/
STS
1
Stop. Indicates that the target is requesting the master to
stop the current transaction. The IXP1250 drives as target
and receives as master.
DEVSEL_L
B13
I2/O2/
STS
1
Device Select. Indicates that the target has decoded its
address as the target of the current access. The IXP1250
drives as target and receives as initiator.
IDSEL
C17
I2
1
Initialization Device Select. Used as Chip Select during PCI
Configuration Space read and write transactions.
PERR_L
D13
I2/O2/
STS
1
Parity error. Used to report data parity errors. The IXP1250
asserts this when it receives bad data parity as target of a
write or master of a read.
SERR_L
E13
I2/O2/
OD
1
System Error.
As an input, it can cause an interrupt to the StrongARM* core
if the IXP1250 is selected for PCI Central Function and
arbitration support (PCI_CFN[1:0]=11).
As an output it can be asserted by the IXP1250 by writing the
SERR bit in the PCI control register, or in response to a PCI
address parity error when not providing PCI Central Function
and arbitration support (PCI_CFN[1:0]=00).
PCI_IRQ_L
B21
I2/O2/
OD
1
PCI Interrupt Request.
As output, used to interrupt the PCI Host Processor. It is
asserted when there is a doorbell set or there are messages
on the I
O outbound post list. This is usually connected to
INTA_L on the PCI Bus.
As Input, It is asserted when there is a doorbell set or there
are messages on the I 2 O outbound post list.
PCI_RST_L
E20
I2/O2/
TS
1
PCI Reset.
When providing PCI Central Function and arbitration
support (PCI_CFN[1:0]=11), PCI _RST_L is an output
controlled by the StrongARM* core. Used to reset the
PCI Bus.
When not providing PCI Central Function and arbitration
(PCI_CFN[1:0]=00), PCI_RST_L is an input, and when
asserted resets the IXP1250 StrongARM* core, all
registers, all transaction queues, and all PCI related
state.
PCI_CLK
D20
I2
1
PCI Clock input. Reference for PCI signals and internal
operations. PCI clock is typically 33 to 66 MHz.
Table 18. PCI Interface Pins (Continued)
PCI Interface
Signal Names
Pin
Number
Type
Total
Pin Descriptions
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