參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 22/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
22
Datasheet
—
The
sram
microinstruction defines the number of 32-bit accesses to make, up to 8
longwords with one Microengine command.
—
Only bit and longword accesses are supported.
—
Bit write accesses result in Read-Modify-Write cycles.
—
Unlike the StrongARM* core, the Microengine microinstruction allows you to perform
bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations,
Lock/Unlock, etc.).
2.6
PCI Unit
The PCI Unit provides an industry standard 32-bit PCI Bus to interface to PCI peripheral devices
such as host processors and MAC devices. The PCI Unit supports operating speeds from DC up to
66 MHz, and supports
PCI Local Bus Specification, Revision 2.2
. This unit contains:
Arbitration logic to support up to three PCI Bus masters,
PCI Intelligent I/O (I
2
O),
Two DMA channels, and
Four 24-bit timers.
Refer to the
IXP1200 Network Processor Family Hardware Reference Manual
for details on PCI
Bus behavior for Target (Slave) and Initiator (Master) modes, configuration and register
definitions.
The PCI interface is specified to operate from DC up to 66 MHz. Above 33 MHz operation, two
PCI devices are supported only, the IXP1250 and a second PCI device. To increase the number of
PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI
bridge device, such the Intel 21150, 21152, or 21153 is required.
Both PCI Initiator and Target cycles are supported. As a target device, the IXP1250 responds as a
Medium Speed device asserting DEVSEL_L two PCI_CLK cycles after FRAME_L is asserted.
2.6.1
PCI Arbitration and Central Function Support
The IXP1250 contains an optional arbiter to support up to three PCI Bus masters. This includes the
IXP1250 plus two external PCI Bus master devices. The external masters are supported by two
request signals, REQ_L[1:0], and two grant signals GNT_L[1:0].
The IXP1250 can also provide PCI Central Function support. In this configuration, the IXP1250:
Drives the PCI Reset signal, PCI_RST_L, as an output,
Monitors the PCI System Error input signal, SERR_L, and
Provides Bus Parking where the IXP1250 is the default PCI Bus master, and it drives valid
logic levels on the PCI A/D, C/BE, and PAR pins during reset and idle PCI Bus conditions.
Two configuration pins, PCI_CFN[1:0], are sampled at the rising edge of RESET_IN_L to
determine the PCI configuration (see
Table 10
)
相關(guān)PDF資料
PDF描述
GCIXP1250-232 Microprocessor
GCK101 Analog IC
GCK131 Microcontroller
GCM-3.15A Fuse
GCM-4A Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GCIXP1250BA 功能描述:IC MPU NETWORK 166MHZ 520-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
GCIXP1250BB 功能描述:IC MPU NETWORK 200MHZ 520-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
GCIXP1250BC 功能描述:IC MPU NETWORK 232MHZ 520-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
GCJ0335C5C0JR50D 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:Chip Monolithic Ceramic Capacitors
GCJ0335C5C1AR50D 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:Chip Monolithic Ceramic Capacitors
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*