參數(shù)資料
型號(hào): GCIXF1002EDT
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 9/128頁
文件大?。?/td> 1262K
代理商: GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
9
1.0
Introduction
1.1
General Description
The Intel
IXF1002 Dual-Port Gigabit Ethernet Controller includes two full-duplex independent
1000 Mb/s Ethernet controllers and interfaces directly to Gigabit Ethernet standard transceivers
through its Gigabit Media Independent Interface (GMII) or GPCS interface. The IXF1002 handles
Simple Network Management Protocol (SNMP) and Remote Monitoring (RMON) management
counter sets, accessible through a generic CPU 8/16-bit interface, which is also used for mode
programming. Each MAC port includes a 4 Kbyte FIFO for packet receive, and a 2 Kbyte FIFO for
packet transmit. All the packets are transferred onto a high-performance, common IX Bus
interface. The IXF1002 CPU and IX Bus interfaces are compatible to the Intel
21440 Octal Fast
Ethernet Controller device.
The IXF1002 is fully compatible with IEEE 802.3x and 802.3z standards, including
Auto-Negotiation and flow-control support.
It is implemented in a low-power 3.3 V CMOS device within a 304-ESBGA package.
1.2
Block Diagram
Figure 1
shows the IXF1002 block diagram.
Figure 1. Block Diagram
A4965-02
Control
Port 0
JTAG
CPU
Bus
FIFO
Bus
(IX Bus)
GPCS/GMII
GPCS/GMII
MGMT
Counts
Receive
FIFO
Transmit
FIFO
Receive
MAC
8B10B
Receive
GPCS
8B10B
Transmit
GPCS
Transmit
MAC
Port 1
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