Intel
IXF1002 Dual Port Gigabit
Ethernet Controller
Datasheet
Product Features
The Intel
IXF1002 Dual Port Gigabit Ethernet Media Access Controller
(MAC), provides two independent 1000 Mb/s intelligent, high-performance
Media Access Control (MAC) ports. It includes Gigabit Physical Coding
Sublayer (GPCS) interface network management support and is optimized for
switch applications.
I
Integration
—
Offers two independent Ethernet 1000 Mb/s
MAC ports
—
Includes GPCS functions for 1000BASE-X
connections
—
Handles SNMP and RMON counters
I
IX Bus
—
Supports up to 5.12 Gbps memory bus
bandwidth
—
Variable bus speed of 33 MHz to 80 MHz
—
64-bit bus with three modes of operation:
Full
—
64 bits for transmit or receive
Split
—
32 low bits for receive, and 32 high
bits for transmit
Narrow
—
32 bits for transmit or receive
—
Independent 2 Kbyte transmit FIFO and 4
Kbyte receive FIFO for each port
—
Supports little or big endian byte ordering
—
Supports receive packet fragmentation on byte
boundaries (replay feature)
—
Programmable transmit and receive bus
thresholds
—
Enables optional appending of packet status
I
Performance
—
Packet transfers are completed prior to
servicing CPU interrupt requests
—
Enables early address filtering ability, with
packet header preprocessing
—
IEEE P802.1Q Virtual Bridged Local Area
Network (VLAN) tag append, strip and
replace function on chip, during packet
transmission
—
Offers ignore or stop transmission options
following packet transmission errors
—
Provides programmable automatic discard of
badly received packets such as cyclic
redundancy (CRC) errors and too long packets
—
Informs the system in case bad packets start to
appear on the FIFO bus
—
Allows interpacket gap (IPG) programming
I
Serial
—
Enables independent mode of operation in
each port
—
Supports IEEE 802.3x standard flow-control
functionality
—
Interfaces standard GPCS connections (10b
interface)
—
Interfaces standard GMII connections
—
Supports 1000BASE-SX, 1000BASE-LX,
1000BASE-CX, and 1000BASE-T
connections
—
Provides programmable CRC generation and
removal
—
Supports Auto-Negotiation link protocol for
1000BASE-X
—
Implements only full-duplex operation
—
Complies with IEEE 802.3z standard
—
Supports large packets of up to 64 Kbytes
I
CPU Interface
—
Supports fully programmable independent
ports through a dedicated generic CPU port
—
Supports interrupt programming
—
Provides an 8- or 16-bit bus for register access
I
Device
—
CPU and FIFO interfaces are compatible with
the IXF440 Multiport 10/100 Mbps Ethernet
Controller and the IXP1200 Network
Processor.
—
Includes internal and external loopback
capabilities
—
Provides software reset support
—
Supports JTAG boundary scan
—
Implemented in a low-power 3.3 V and 5 V
tolerant CMOS device
—
304-ESBGA package.
Order Number: 278310-008
June, 2002
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.