參數資料
型號： GCIXF440AC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數據表參考
文件頁數： 84/128頁
文件大?。?/td> 1262K
代理商： GCIXF440AC
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
84
Datasheet
In GPCS mode, the transmitted packets pass through the GPCS encoding and decoding logic, and
the txd<7:0> signals are unpredictable.
6.6.2
External Loopback Mode
The external loopback mode enables verification that the logic up to the wire operates correctly. In
GPSC mode, when setting the external loopback mode (MII_CTL<LPBK>), the ewrap_{i} signal
will be asserted in order to cause the external logic to loop back frames from the transmit side to
the receive side. In GPCS mode, the loopback will work properly even if the link detection signal
(sd) is not asserted.
In GMII mode, external loopback mode could be enabled by programming the external logic PHY
to loop back frames from the transmit side to the receive side.
6.7
GPCS Mode
In the GPCS mode (PORT_MODE<GPCS=1>), the 8B/10B PCS encoding and decoding is
performed by the IXF1002. The functions implemented in this mode include:
8-bit to 10-bit encoding in the transmit path
10-bit to 8-bit decoding in the receive path
Auto-Negotiation
Start-of-packet delimiter (SOP) and end-of-packet delimiters (EOP) detection and generation
Symbol error detection
Link timer
In the GPCS mode, the GMII/GPCS port works as a GPCS port.
Table 14
describes the GPCS port
signal names and their appropriate functions.
Table 14. GPCS Port Signal Description (Sheet 1 of 2)
GPCS Signals
IEEE 802.3z
Signals
—
PMA_TX_CLK
I/O Description
tclk
pmatclk_{i}
I
O
Input - 125 MHz clock for reference.
125 MHz transmit clock, synchronizing the txd_{i}<9:0> signals.
The 62.5 MHhz recovered receive byte clock. Used to latch odd
numbered bytes of the receive data.
The 62.5 MHz recovered receive byte clock. This clock is 180
°
out-of-phase with rclk_{i}, and is used to latch even numbered
bytes of the receive data.
Transmit data lines, driving a symbol on each tclk cycle.
Receive data lines, driving a symbol on each pmarclk_0 and
pmarclk_1 positive edge.
Link signal, asserted by the IXF1002 when the GPCS logic detects
a link to a remote node.
Signal detect, asserted by the PHY layer when it detects link
connection to the remote mode.
Activity signal, asserted by the IXF1002 when it transmits a frame
or is receiving a frame.
rclk_{i}
PMA_RX_CLK0
I
pmarclk_{i}
PMA_RX_CLK1
I
txd_{i}<9:0>
TX_CODE-GROUP
O
rxd_{i}<9:0>
RX_CODE-GROUP I
lnk_{i}
—
O
sd{i}
SIGNAL_DETECT
I
act_{i}
—
O
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