參數(shù)資料
型號： GCIXF440AC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 5/128頁
文件大?。?/td> 1262K
代理商： GCIXF440AC
Datasheet
v
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Transmit Initiation...................................................................................80
Inter Packet Gap ....................................................................................80
Frame Encapsulation .............................................................................80
Terminating Transmission......................................................................80
Flow Control...........................................................................................81
6.4.5.1 Additional Flow-Control Mode ...................................................81
MAC Receive Operation......................................................................................82
6.5.1
Receive Initiation....................................................................................82
6.5.2
Preamble Processing .............................................................................82
6.5.3
Frame Decapsulation .............................................................................82
6.5.4
Terminating Reception ...........................................................................82
6.5.5
Flow Control...........................................................................................83
MAC Loopback Operations.................................................................................83
6.6.1
Internal Loopback Mode.........................................................................83
6.6.2
External Loopback Mode........................................................................84
GPCS Mode........................................................................................................84
6.7.1
Synchronization......................................................................................86
6.7.1.1 Comma detect...........................................................................86
6.7.2
Auto-Negotiation.....................................................................................86
6.5
6.6
6.7
7.0
Timing Diagrams..............................................................................................................87
7.1
IX Bus Port Timing Diagrams..............................................................................87
7.1.1
Transmit Start-of-Packet Timing.............................................................87
7.1.2
Transmit End-of-Packet Timing..............................................................88
7.1.3
Transmit Packet Timing in Split Mode....................................................88
7.1.4
Transmit Packet with VLAN Tag Append Timing ...................................89
7.1.5
VLAN Strip Mode Timing........................................................................90
7.1.6
Transmit Packet with VLAN Tag Replace Timing ..................................91
7.1.7
VLAN Tag Append in Two txsel_l Bursts ...............................................92
7.1.8
VLAN Tag Replace in Two txsel_l Bursts...............................................93
7.1.9
Transmit FIFO Control Timing................................................................93
7.1.10 Transmit txrdy Timing.............................................................................94
7.1.11 Receive Start-of-Packet Timing..............................................................94
7.1.12 Receive End-of-Packet Timing...............................................................95
7.1.13 Receive Packet Timing in Split Mode.....................................................96
7.1.14 Receive rxfail Timing..............................................................................97
7.1.15 Receive rxabt Timing..............................................................................98
7.1.16 Receive rxkep Timing.............................................................................99
7.1.17 Receive Header Replay Timing............................................................100
7.1.18 Receive FIFO Control Timing...............................................................100
7.1.19 Receive rxrdy Control Timing...............................................................101
7.1.20 Consecutive Transmit-Transmit Timing................................................101
7.1.21 Consecutive Transmit-Receive Timing.................................................102
7.1.22 Consecutive Receive-Transmit Timing.................................................102
7.1.23 Consecutive Receive-Receive Timing..................................................103
7.2
GMII/GPCS Port Timing Diagrams....................................................................103
7.2.1
Packet Transmission Timing ................................................................103
7.2.2
Packet Reception Timing .....................................................................104
7.2.3
False Carrier Timing.............................................................................104
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GCIXF440ACT 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述:
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GCIXP1200FC 功能描述:IC NETWRK PROCESSR 232MHZ 432BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
GCIXP1200GA 功能描述:IC MPU NETWORK 166MHZ 432-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
GCIXP1200GB 功能描述:IC MPU NETWORK 200MHZ 432-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
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