參數(shù)資料
型號(hào): GCIXF440AC
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 33/128頁
文件大?。?/td> 1262K
代理商: GCIXF440AC
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
33
LCKE
7
Enable activation of lock to reference signal.
When set, the lckref_{i} signal will be
asserted to the PHY when there is no activity (no signal detected) on the line. Used only in
GPCS mode.
FXECD
6
Fix enable comma detect signal.
When set, the encdet_{i} signal to the PHY will be continuously asserted. When cleared,
the encdet_{i} signal will be asserted only during loss of synchronization. Used only in
GPCS mode.
ILPK
5
Internal loopback mode.
When set, the port is disconnected from the line and all the transmitted packets are sent
back to the receive side. Packets are not transmitted onto the line and packets received
from the line are rejected.
4:3
RESERVED
CPUBW
2
CPU data bus width.
When asserted, bus width is 16, all
cdat<15:0>
bits are in use.
When deasserted, bus width is 8, indicating that the 8 low bits
cdat<7:0>
are in use.
SDDIS
1
Signal detect disable.
Setting this bit will cause IXF1002 to consider the value of the sd{i} input signal as high,
regardless to the actual value on the pin. Used only in GPCS mode.
GPCS
0
GPCS port mode.
This bit defines the GMII/GPCS port mode. If a GPCS PHY device is connected, this bit
must be set. If a GMII PHY device is connected, this bit must be reset.
Access Rules
Register
access
R/W
Value
after
reset
0000H
Bit Name
Bit #
Bit Description
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相關(guān)代理商/技術(shù)參數(shù)
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