參數(shù)資料
型號(hào): GCIXF1002EDT
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 24/128頁
文件大?。?/td> 1262K
代理商: GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
24
Datasheet
3.2.2.2
Interrupt Enable Register
Mnemonic: INT_EN
Address: 02H
03H
Each bit in this register, when set to 1, enables the generation of an interrupt when the
corresponding event occurs. The event causing the interrupt will be reported in the interrupt status
register (INT_STT).
3.2.2.3
Port Control Register
Mnemonic: PORT_CTR
Address: 04H
05H
Access Rules
Register
access
Value
after reset
R
0000H
Bit Name
Bit #
Bit Description
Bit Name
Bit #
Bit Description
15
RESERVED
STOPE
14
Port stop interrupt enable.
OVFCE
13
Counter overflow interrupt enable.
LNCHE
12
Link change interrupt enable.
11
RESERVED
TXOKE
10
Transmit OK interrupt enable.
PKEVE
9
Packet event interrupt enable.
RXOKE
8
Receive OK interrupt enable.
ANERE
7
Auto-Negotiation error interrupt enable.
PGRCE
6
Page received interrupt enable.
5:0
RESERVED
Access Rules
Register
access
R/W
Value
after
reset
0000H
A4967-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
T
O
P
E
O
V
F
C
E
L
N
C
H
E
T
X
O
K
E
P
K
E
V
E
R
X
O
K
E
A
N
E
R
E
P
G
R
C
E
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