參數(shù)資料
型號: GCIXF1002EDT
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 39/128頁
文件大?。?/td> 1262K
代理商: GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
39
3.2.3.11
Transmit Counter Overflow Mask Register
Mnemonic: TX_OV_MSK
Address: 38H
3BH
The transmit counter overflow mask register enables masking of specific transmit counters
overflow interrupt. Masking a counter does not influence the setting of the counter overflow status
bit in TX_OV_STT.
Access Rules
Register
access
R/W
Value after
reset
8100H
Bit Name
Bit #
Bit Description
Bit Name
Bit #
Bit Description
31:20
RESERVED
TX_BD
19
Mask TX_OCT_BAD_CNT counter overflow.
TX_OK
18
Mask TX_OCT_OK_CNT counter overflow.
TX_ER
17
Mask TX_ERR_CNT counter overflow.
TX_PS
16
Mask TX_PAUSE_CNT counter overflow.
TX_1519
15
Mask TX_PKT_1519_CNT counter overflow.
TX_1024
14
Mask TX_PKT_1024_CNT counter overflow.
TX_512
13
Mask TX_PKT_512_CNT counter overflow.
TX_256
12
Mask TX_PKT_256_CNT counter overflow.
TX_128
11
Mask TX_PKT_128_CNT counter overflow.
TX_65
10
Mask TX_PKT_65_CNT counter overflow.
TX_64
9
Mask TX_PKT_64_CNT counter overflow.
8:3
RESERVED
TX_BRD
2
Mask TX_BRD_OK_CNT counter overflow.
TX_MLT
1
Mask TX_MLT_OK_CNT counter overflow.
TX_UNI
0
Mask TX_UNI_OK_CNT counter overflow.
A4983-01
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
30
31
29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
T
X
_
U
N
I
T
X
_
M
L
T
T
X
_
6
5
T
X
_
6
4
T
X
_
B
R
D
T
X
_
1
2
8
T
X
_
2
5
6
T
X
_
5
1
2
T
X
_
1
0
2
4
T
X
_
1
5
1
9
T
X
_
P
S
T
X
_
E
R
T
X
_
O
K
T
X
_
B
D
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