參數(shù)資料
型號： GCIXF1002EDT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 85/128頁
文件大?。?/td> 1262K
代理商： GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
85
When operating in the GPCS mode, the IXF1002 encapsulates and decapsulates the frames
according to the IEEE 802.3z 1000BASE-X standard.
During transmit, encapsulation is performed according to the following rules:
The first byte of the preamble in the MAC frame is replaced with the /S/ symbol.
All of the MAC frame data is encoded according to 8B/10B standard encoding.
After the FCS byte of the MAC frame, the /T/R/R/ or /T/R/ symbol is inserted.
An IDLE symbol /I/, is transmitted between frames.
Transmit error generation is translated to illegal symbol generation.
During receive, decapsulation is performed according to the following rules:
An /I/S/ symbol sequence will cause the internal data valid signal to be asserted (start of
receive activity).
The /S/ symbol is replaced by a preamble byte.
All of the data symbol stream is decoded according to 10B/8B standard decoding.
The /T/R/R/ or/T/R/ symbol sequence will cause the internal data valid signal to be deasserted
(end of receive activity).
During receive, the IXF1002 expects the frame to start with the symbol sequence /I/S/ followed by
the preamble. If an /I/S/ symbol sequence is not detected, the reception of the current frame is
aborted (not received), and the IXF1002 waits until the network activity stops before monitoring
the network activity for a new frame. During reception, the IXF1002 also checks symbol validity.
If an invalid symbol is being received, or if the frame does not end with the /T/R/R/ or /T/R/
symbol sequence, the IXF1002 reports a receive error.
ewrap_{i}
EWRAP
O
Enable Warp.
When asserted to the PHY, it should loop the transmit serialized
data to the receive section. This pin is controlled in the GMII
management control register (MII_CTL<LPBK>).
Lock to reference.
When asserted, enables the PHY to lock its PLL to the 125 MHz
reference clock. This pin is controlled by bit LCKE in the
PORT_MODE register.
Enable comma detect.
When asserted, enables the PHY for comma detect and word
resynchronization. When deasserted, the PHY will keep current
word alignment and will not try to detect new commas.
Comma detect.
An indication from the PHY layer that the data contains a valid
comma character.
lckref_l_{i}
LCK_REF
O
encdet_{i}
EN_CDET
O
comdet_{i}
COM_DET
I
Table 14. GPCS Port Signal Description (Sheet 2 of 2)
GPCS Signals
IEEE 802.3z
Signals
I/O Description
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