參數(shù)資料
型號: GCIXF1002EDT
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 10/128頁
文件大?。?/td> 1262K
代理商: GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
10
Datasheet
1.3
Hardware Overview
Table 1
describes the IXF1002 components.
Table 1. Component Description
Component
Description
Transmit FIFO
A 2 Kbyte buffer for temporary storage of transmitted packets. The transmit FIFO
has direct interface to the IX Bus.
Receive FIFO
A 4 Kbyte buffer for temporary storage of received packets. Supports packet
deletion in case of errors. The receive FIFO has direct interface to the IX Bus.
Transmit MAC
Implements the IEEE 802.3 transmit full-duplex MAC functions while interfacing
between the transmit FIFO and the GMII PHY or the GPCS function.
Receive MAC
Implements the IEEE 802.3 receive full-duplex MAC functions while interfacing
between the receive FIFO and the GMII PHY or the GPCS function.
GPCS
Implementing the 1000BASE-X PCS layer that includes the Auto-Negotiation
synchronization and encoding/decoding functions.
SNMP and RMON
Handles network statistic counters for SNMP and RMON.
Control
Handles the chip registers accessible through the CPU bus.
JTAG
Includes the JTAG technologies IEEE 1149.1 (JTAG) boundary scan logic.
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