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參數(shù)資料
| 型號(hào)： | GCIXF1002EDT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 127/128頁(yè) |
| 文件大小： | 1262K |
| 代理商： | GCIXF1002EDT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
127
Bit Name
Bit #
Bit Description
—
15
RESERVED
—
14
RESERVED
Should be written to 0 for future compability.
MLTPKT
13
Multi-Packet Mode.
When set, the device operates in Multi-Packet mode. While working in Multi-Packet mode,
the txrdy signal is deasserted when at least one of the following is true:
The amount of free space in its TFIFO is below the FIFO transmit threshold.
The number of full packets stored in the TFIFO is sixteen.
A data burst on the IX Bus is in progress.
Note that the Single Packet Mode control bit (TX_RX_PARAM<SPM>) should be reset to
0 when this bit is set.
When cleared, the device retains all the features as described in the
IXF1002Dual Port
Gigabit Ethernet Datasheet
.
FIFMD
12:11
IX Bus mode:
This field sets the IX Bus mode. Both ports of the IXF1002 must be operating in the same
IX Bus mode. The table below shows the IX Bus mode according to bits 12 and 11.
Bit 12
Bit 11
Mode
0
0
Narrow-32 bit mode
0
1
Full-64 bit mode
1
0
Split mode
1
1
Reserved
In the full-64 bit mode, the 64 bits fdat<63:0> are used for either transmitting or receiving
data.
In the split mode, the 32 lower bits fdat<31:0> are used for receiving packets from the
receive FIFO and the 32 higher bits fdat<63:32> are used for transmitting packets to the
transmit FIFO.
In the narrow mode, the lower 32 bits fdat<31:1> are used for either transmitting or
receiving packets.
HRYD
10
Header ready disable.
When set, the
rxrdy
signal will not be asserted when a packet header is in FIFO, but only
according to FIFO threshold values.
PS_D
9
Packet status disable.
When set, the packet status will not be appended to received packets that are transferred
onto the IX Bus. When reset, The packet status is appended to any packet completely
transferred onto the IX Bus, and is driven onto the IX Bus in the access following the last
byte transfer (
see 4.3.1.1
) of data.
BEND
8
Big or little endian mode.
Defines the byte ordering mode on the IX Bus. When set, the port uses the big endian
mode. When reset, the little endian mode is used.
A4975-02
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
H
R
Y
D
M
L
T
P
K
T
P
S
–
D
B
E
N
D
L
C
K
E
F
X
E
C
D
I
L
P
K
F
I
F
M
D
G
P
C
S
S
D
D
I
S
C
P
U
B
W
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