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| 型號(hào)： | GCIXF1002EDT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 12/128頁(yè) |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF1002EDT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
12
Datasheet
cdat<15:0>
I/O
CPU data bus.
In 8 bit mode (default):
cdat<7:0> carries data to be written to or read from the registers.
cdat<15:8> should be connected to pull up resistors.
In 16 bit mode:
cdat<15:0> carries data to be written to or read from the registers.
Interrupt lines.
These signals are asserted following a variety of programmable conditions.
Deassertion occurs after reading the events that cause the interrupt, unless
another interrupt is registered meanwhile.
General reset.
Upon reset, all the registers are reset to their default values and the FIFOs are
flushed.
reset_l assertion time should be at least 1 ms.
cint{i}_l
OD
reset_l
I
IX Bus Interface
clamp
I
Vdd clamp.
Should be connected to the power of the highest signal level used on the IX Bus.
System clock.
All the FIFO data transfers are synchronized to this clock.
Transmit select.
This pin must be asserted to enable transmit FIFO write access.
Receive select.
This pin must be asserted to enable receive FIFO read access. The following
signals are driven by the IXF1002 upon assertion of rxsel_l:
FIFO port select.
In full-64 mode and in narrow mode (fps):
When asserted, selects port no. 1 for data transfer through the IX Bus.
When deasserted, selects port no. 0 for data transfer through the IX Bus.
In split mode(fps_rxf):
Selects one of the ports for reading data, through fdat<31:0>, from the
receive FIFO of the selected port.
FIFO port select.
In full-64 mode and in narrow mode:
Not in use, should be connected to pull up resistors.
In split mode:
Selects one of the ports for writing data, through fdat<63:32>, to the transmit
FIFO of the selected port.
clk
I
txsel_l
I
rxsel_l
I
fdat<63:0>, fbe_l<7:0>, sop, eop and rxfail in full-64 IX Bus mode
.
fdat<31:0>, fbe_l<3:0>, sop_rxf, eop_rxf and rxfail in split IX Bus mode
.
fdat<31:0>, fbe_l<3:0>, sop, eop and rxfail in narrow IX Bus mode
.
fps/fps_rxf
I
fps_txf
I
Table 2. Signal Descriptions (Sheet 2 of 6)
Signal Name
I/O
Pin Description
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