參數(shù)資料
型號： GCIXF1002EDT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 71/128頁
文件大?。?/td> 1262K
代理商： GCIXF1002EDT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
71
4.3.4
Packet Abortion
During the transfer of a received packet onto the IX Bus, the IXF1002 supports the ability to
prevent any further transfer of this packet. At any time during packet reception, the packet may be
dynamically discarded from the receive FIFO by asserting the rxabt signal during packet reading
while rxsel_l signal is asserted. Any subsequent packet loaded onto the receive FIFO is not affected
by rxabt assertion. The next FIFO access will access the new packet.
4.3.5
Network Reception
A packet received from the network is loaded to the receive FIFO. If the packet is received without
any error, it is transferred to the IX Bus. If an error occurs during reception, the packet is handled
according to the programming in the TX_RX_ERR register.
The IXF1002 may be programmed to work in two modes: reject the erroneous packet or accept it.
In both modes, the appropriate statistic counters will be updated (even if the packet was rejected
due to packet error or FIFO overflow), and any following packets will continue to be accepted and
loaded to the receive FIFO.
The following events are considered as reception errors:
FIFO overflow
CRC error
Short packet
Too long packet
GMII error
4.3.6
Rejecting Mode on Reception Errors
If a packet with a reception error is programmed to be rejected (zero in the relevant bit of the
TX_RX_ERR register). The IXF1002 discards the packet from the receive FIFO without affecting
previous packets that may still be in the receive FIFO. If the packet had not yet started to be
transferred on the IX Bus, it will be discarded without affecting IX Bus activity. If the packet had
already started to be transferred onto the IX Bus, or rxrdy was already asserted, the rxfail signal
will be asserted on the next FIFO access, indicating that the currently transferred packet was
discarded from the receive FIFO. Packet status will not be driven for such a packet.
4.3.7
Accepting Mode on Reception Errors
If a packet with a reception error is programmed to be accepted, (a 1 in the relevant bit of the
TX_RX_ERR register), it is transferred to the IX Bus as a regular packet. The event type is
reported in the packet status appended to the end of the packet, and in the transmit and receive
status register (TX_RX_STT).
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