82371AB (PIIX4)
E
44
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
3.1.2.
IO SPACE REGISTERS
Table 5. ISA-Compatible Registers
Address
Aliased
Addresses
Type
Register Name
Access
0000h
0010h
R/W
DMA1 CH0 Base and Current Address (CH0)
PCI
0001h
0011h
R/W
DMA1 CH0 Base and Current Count (CH0)
PCI
0002h
0012h
R/W
DMA1 CH1 Base and Current Address (CH1)
PCI
0003h
0013h
R/W
DMA1 CH1 Base and Current Count (CH1)
PCI
0004h
0014h
R/W
DMA1 CH2 Base and Current Address (CH2)
PCI
0005h
0015h
R/W
DMA1 CH2 Base and Current Count (CH2)
PCI
0006h
0016h
R/W
DMA1 CH3 Base and Current Address (CH3)
PCI
0007h
0017h
R/W
DMA1 CH3 Base and Current Count (CH3)
PCI
0008h
0018h
R/W
DMA1 Status(r) Command(w) Register
PCI
0009h
0019h
WO
DMA1 Request
PCI
000Ah
001Ah
WO
DMA1 Write Single Mask Bit
PCI
000Bh
001Bh
WO
DMA1 Channel Mode
PCI
000Ch
001Ch
WO
DMA1 Clear Byte Pointer
PCI
000Dh
001Dh
WO
DMA1 Master Clear
PCI
000Eh
001Eh
WO
DMA1 Clear Mask
PCI
000Fh
001Fh
R/W
DMA1 Read/Write All Mask Bits
PCI
0020h
0024h, 0028h,
002Ch, 0030h,
0034h, 0038h,
003Ch
R/W
Initialization Command Word 1 (INT-1)
Operational Command Word 2 (INT-1)
Operational Command Word 3 (INT-1)
PCI/ISA
0021h
0025h, 0029h,
002Dh, 0031h,
0035h, 0039h,
003Dh
R/W
Initialization Command Word 2 (INT-1)
Initialization Command Word 3 (INT-1)
Initialization Command Word 4 (INT-1)
Operational Command Word 1 (INT-1)
PCI/ISA
0040h
0050h
R/W
Timer Count – Counter 0
Timer Status – Counter 0 (RO)
PCI/ISA
0041h
0051h
R/W
Timer Count – Counter 1
Timer Status – Counter 1 (RO)
PCI/ISA
0042h
0052h
R/W
Timer Count – Counter 2
Timer Status – Counter 2 (RO)
PCI/ISA
0043h
0053h
WO
Timer Control Word
PCI/ISA
0060h
1
RO
Reset X-Bus IRQ12/M and IRQ1
PCI/ISA
0061h
0063h, 0065h,
0067h
R/W
NMI Status and Control
PCI/ISA