E
7.1.11.
82371AB (PIIX4)
121
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
CNTA—COUNT A (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
44–47h
00h
Read/Write
This register contains the initial counts of the idle timers for devices 0–11, the selection bits for the timer
granularity of the timers for devices 0, 1, 2 and 3. In addition, it contains the count for the slow burst timer.
Bit
Description
31:28
Slow Burst Count (SB_CNT)—R/W.
Specifies the initial and reload value of the slow burst timer.
27:23
Idle Timer Count D (IDL_CNTD)—R/W.
Specifies the initial and reload count of the device 11 (user
interface) idle timer.
22
Device 11 Idle Timer Resolution (IDL_SEL_DEV11)—R/W.
Selects the clock resolution of the
device 11 (user interface) idle timer. 0=1 second granular. 1=1 minute granular.
21:17
Idle Timer Count C (IDL_CNTC)—R/W.
Specifies the initial and reload count of the device 9–10
(generic range) idle timers.
16:12
Idle Timer Count B (IDL_CNTB)—R/W.
Specifies the initial and reload count of the device 4–7
(audio, floppy, serial ports, parallel port) idle timers.
11:8
SW Idle Timer Count (SW_CNT)—R/W.
Specifies the initial and reload count of the device 3
(secondary IDE drive 1, software SMI) idle timer.
7
Device 3 Idle Timer Resolution (IDL_SEL_DEV3)—R/W.
Selects the clock source for the
device 3 (secondary IDE drive 1, software SMI) idle timer. 0=8 second granular. 1=1 ms granular.
6
Device 2 Idle Timer Resolution (IDL_SEL_DEV2)—R/W.
Selects the clock source for the
device 2 (secondary IDE drive 0) idle timer. 0=8 second granular. 1=1 second granular.
5
Device 1 Idle Timer Resolution (IDL_SEL_DEV1)—R/W.
Selects the clock source for the
device 1 (primary IDE drive 1) idle timer. 0=8 second granular. 1=1 second granular.
4
Device 0 Idle Timer Resolution (IDL_SEL_DEV0)—R/W.
Selects the clock source for the
device 0 (primary IDE drive 0) idle timer. 0=8 second granular. 1=1 second granular.
3:0
Idle Timer Count A (IDL_CNTA)—R/W.
Specifies the initial and reload count of the device 0–2
(primary IDE drives 0 and 1, secondary IDE drive 0) idle timers.
7.1.12.
CNTB—COUNT B (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
48–4Bh
00h
Read/Write
This register contains the counts for Fast Burst Timer, the CPU select and lock bits, the thermal duty cycle
programming bits, the ZZ enable bits, the clock granularity selection for device 8, and the Video Status bit.
Bit
Description
31:25
Reserved.
Read as 0.
24
Video Status (VID_STS)—R/WC.
1=The PCI bus utilization monitor has detected PCI activity which
exceeds its defined threshold (see description for Device Monitor 11).
This bit is set by hardware and
reset by
writing a 1 to this bit position.