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參數(shù)資料
| 型號(hào)： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁(yè)數(shù)： | 19/284頁(yè) |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
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E
82371AB (PIIX4)
19
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name
Type
Description
IOCHRDY
I/O
I/O CHANNEL READY.
Resources on the ISA Bus negate IOCHRDY to indicate that
wait states are required to complete the cycle. This signal is normally high. IOCHRDY
is an input when PIIX4 owns the ISA Bus and the CPU or a PCI agent is accessing an
ISA slave, or during DMA transfers. IOCHRDY is output when an external ISA Bus
Master owns the ISA Bus and is accessing DRAM or a PIIX4 register. As a PIIX4
output, IOCHRDY is driven inactive (low) from the falling edge of the ISA commands.
After data is available for an ISA master read or PIIX4 latches the data for a write
cycle, IOCHRDY is asserted for 70 ns. After 70 ns, PIIX4 floats IOCHRDY. The 70 ns
includes both the drive time and the time it takes PIIX4 to float IOCHRDY. PIIX4 does
not drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset:
High-Z
After Reset:
High-Z
During POS:
High-Z
IOCS16#
I
16-BIT I/O CHIP SELECT.
This signal is driven by I/O devices on the ISA Bus to
indicate support for 16-bit I/O bus cycles.
IOR#
I/O
I/O READ.
IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus (SD[15:0]). The I/O slave device must hold the data valid
until after IOR# is negated. IOR# is an output when PIIX4 owns the ISA Bus. IOR# is
an input when an external ISA master owns the ISA Bus.
During Reset:
High-Z
After Reset:
High
During POS:
High
IOW#
I/O
I/O WRITE.
IOW# is the command to an ISA I/O slave device that the slave may latch
data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA
Bus. IOW# is an input when an external ISA master owns the ISA Bus.
During Reset:
High-Z
After Reset:
High
During POS:
High
LA[23:17]/
GPO[7:1]
I/O
ISA LA[23:17].
LA[23:17] address lines allow accesses to physical memory on the
ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the ISA Bus. The
LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus.
If the EIO bus is used, these signals become a general purpose output.
During Reset:
High-Z
After Reset:
Undefined
During POS:
Last LA/GPO
MEMCS16#
I/O
MEMORY CHIP SELECT 16.
MEMCS16# is a decode of LA[23:17] without any
qualification of the command signal lines. ISA slaves that are 16-bit memory devices
drive this signal low. PIIX4 ignores MEMCS16# during I/O access cycles and refresh
cycles. MEMCS16# is an input when PIIX4 owns the ISA Bus. PIIX4 drives this signal
low during ISA master to PCI memory cycles.
During Reset:
High-Z
After Reset:
High-Z
During POS:
High-Z
MEMR#
I/O
MEMORY READ.
MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus. MEMR# is an output when PIIX4 is a master on the ISA Bus.
MEMR# is an input when an ISA master, other than PIIX4, owns the ISA Bus. This
signal is also driven by PIIX4 during refresh cycles. For DMA cycles, PIIX4, as a
master, asserts MEMR#.
During Reset:
High-Z
After Reset:
High
During POS:
High
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW82801E | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
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