82371AB (PIIX4)
E
268
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
11.6.
ACPI Support
PIIX4 supports the ACPI I/O Register mapping, the SCI interrupt and the Power Management Timer. PIIX4 also
supports a semaphore mechanism to coordinate access to the power management resources by either ACPI or
the BIOS.
11.6.1.
SCI GENERATION
The THRM#, GPI1#, LID, and PWRBTN# can be enabled to generate the ACPI interrupt, SCI (internal IRQ9) or
an SMI#. The SMI# or SCI is selectable with the [SCI_EN] bit. When set to 1, these events generate an SCI, if
enabled. When reset, these events generate an SMI#, if enabled. See the “System Management” section for
additional details on SMI and the THRM#, GPI1#, LID and PWRBTN# events.
SCI Generation Events
PWRBTN# Asserted:
LID Asserted:
[PWRBTN_EN]
[LID_EN]
[LID_POL]
[GPI_EN]
[THRM_EN]
[THRM_POL]
— Polarity Select:
GPI1 Asserted:
Thermal Alarm (THRM# Assertion):
— Polarity Select:
Power Management Timer Expiration:
[TMROF_EN]
BIOS Release:
[GBL_EN]
11.6.2.
POWER MANAGEMENT TIMER
A power management timer is used by the OS to evaluate when the system is idle. The timer consists of a
constantly running time base (14.31818 MHz/4 or 3.579545 MHz), a running time base value, and a single
interrupt source (Figure 33). The interrupt source indicates that the counter has changed bit 23 (high to low or
low to high); this condition generates a System Control Interrupt (SCI). The overflow interrupt is used by
software to understand when the timer is about to overflow, and allows software to emulate a much
larger timer.
24-bit
Counter
Bits [23:0]
PM Timer
State Machine
PM1_STS.0
TMROF_EN
PM1_EN.0
TMR_VAL
PM1_TMR.[23:0]
3.579545 MHz
24
pwr_tim
Figure 33. Power Management Timer