E
7.1.13.
82371AB (PIIX4)
123
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
GPICTL—GENERAL PURPOSE INPUT CONTROL (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
4C–4Fh
00h
Read/Write
This register contains the enable bits, the polarity bits and edge selection bits for the General Purpose IO in
device monitors 1–13.
Bit
Description
31:28
Reserved.
27
GPI Edge Select (GPI_EDG_DEV13)—R/W.
Selects edge or level sensitivity of device monitor 13
GPI signal. 0=level. 1=edge.
26
GPI Edge Select (GPI_EDG_DEV12)—R/W.
Selects edge or level sensitivity of device monitor 12
GP signal. 0=level. 1=edge.
25:13
GPI Polarity Select (GPI_POL_DEV[1:13])—R/W.
Selects the assertion polarity for an enabled GPI
signal for device monitors 1–13. 0=Asserted high. 1=Asserted low.
Bit 25 corresponds to device
monitor 13 and bit 13 corresponds to device monitor 1.
12:0
GPI Enable (GPI_EN_DEV[1:13])—R/W.
1=Enable the device monitor’s GPI signal into the trap and
idle decode logic for devices [13:1]. 0=Disable. Bit 12 corresponds to device monitor 13 and bit 0
corresponds to device monitor 1.
Table 17 illustrates which GPI signals correspond with which device.
Table 17. GPI to Device Monitor Translation
Device Monitoring
Optional GPI Signal
Device Monitoring
Optional GPI Signal
DEV0
None
DEV7
GPI16
DEV1
GPI5
DEV8
GPI17
DEV2
GPI6
DEV9
GPI4
DEV3
GPI0
DEV10
GPI18
DEV4
GPI13
DEV11
GPI19
DEV5
GPI14
DEV12
GPI20
DEV6
GPI15
DEV13
GPI21
7.1.14.
DEVRESD—DEVICE RESOURCE D (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
50–52h
00h
Read/Write
This register contains the event enable bits for DMA channels 0,1,3,5,6,7. It also contains the floppy disk
controller monitor enable bit, serial port monitor enable bits, Device 11 IRQ1 monitor enable bit, Device 11
IRQ12 monitor enable bit and LPT DMA select bits.