82371AB (PIIX4)
E
36
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name
Type
Description
GPO[30:0]
O
GENERAL PURPOSE OUTPUTS.
These output signals can be controlled via the
GPIREG register located in Function 3 (Power Management) System IO Space at
address PMBase+34h.
If a GPO pin is not multiplexed with another signal or defaults to GPO, then its state after
reset is the reset condition of the GPOREG register. If the GPO defaults to another
signal, then it defaults to that signal’s state after reset.
The GPO pins that default to GPO remain stable after reset. The others may toggle due
to system boot or power control sequencing after reset prior to their being programmed
as GPOs.
The GPO8 signal is driven low upon removal of power from the PIIX4 core power plane.
All other GPO signals are invalid (buffers powered off).
Table 1. GPI Signals
Signal
Name
Multiplexed
With
Default
Control Register and
Bit (PCI Function 1)
Notes
GPI0
IOCHK#
GPI
GENCFG
Bit 0
Available as GPI only if in EIO bus
mode.
Non-multiplexed GPI which is always
available. This signal when used by
power management logic is active
low.
Not available as GPI if used for
PC/PCI. Can be individually enabled,
so for instance, GPI[4] is available if
REQ[C]# is not used.
Not available as GPI if using an
external APIC.
Not available as GPI if using external
RTC or external APIC.
Not available as GPI if using Serial
IRQ protocol.
Not available as GPI if using thermal
monitoring.
Not available as GPI if using battery
low feature.
Not available as GPI if using LID
feature.
Not available as GPI if using
SMBALERT feature
Not available if using ring indicator
feature
Non-multiplexed GPIs which are
always available.
GPI1#
GPI
GPI[2:4]
REQ[A:C]#
GPI
GENCFG
Bits 8–10
GPI5
APICREQ#
GPI
XBCS
Bit 8
GENCFG
Bit 14
GENCFG
Bit 16
GENCFG
Bit 23
GENCFG
Bit 24
GENCFG
Bit 25
GENCFG
Bit 15
GENCFG
Bit 27
GPI6
IRQ8#
GPI
GPI7
SERIRQ
GPI
GPI8
THRM#
THRM#
GPI9
BATLOW#
BATLOW#
GPI10
LID#
LID
GPI11
SMBALERT#
SMBALERT#
GPI12
RI#
RI#
GPI[13:21]
GPI