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參數(shù)資料
| 型號： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁數(shù)： | 183/284頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
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E
The Read Back Command may be used to latch multiple counter output latches (OL) by setting the COUNT# bit
D5=0 and selecting the desired counter(s). This single command is functionally equivalent to several counter
latch commands, one for each counter latched. Each counter’s latched count is held until it is read (or the
counter is reprogrammed). Once read, a counter is automatically unlatched. The other counters remain latched
until they are read. If multiple count Read Back Commands are issued to the same counter without reading the
count, all but the first are ignored (i.e. the count which will be read is the count at the time the first Read Back
Command was issued).
82371AB (PIIX4)
183
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
The Read Back Command may also be used to latch status information of selected counter(s) by setting
STATUS# bit D4=0. Status must be latched to be read. The status of a counter is accessed by a read from that
counter’s I/O port address.
If multiple counter status latch operations are performed without reading the status, all but the first are ignored.
The status returned from the read is the counter status at the time the first status Read Back Command was
issued.
Both count and status of the selected counter(s) may be latched simultaneously by setting both the COUNT#
and STATUS# bits [5:4]=00. This is functionally the same as issuing two consecutive, separate Read Back
Commands. The above discussions apply here also. Specifically, if multiple count and/or status Read Back
Commands are issued to the same counter(s) without any intervening reads, all but the first are ignored.
If both count and status of a counter are latched, the first read operation from that counter will return the latched
status, regardless of which was latched first. The next one or two reads (depending on whether the counter is
programmed for one or two type counts) return the latched count. Subsequent reads return unlatched count.
8.9.
Real Time Clock
The Real Time Clock (RTC) module provides a date-and-time keeping device with alarm features and battery
backed-up operation. The RTC counts seconds, minutes, hours, days, day of the week, date, month, and year
with leap year compensation. Daylight savings compensation is options. Three interrupt features are available:
time of day alarm with once a second to once a month range, periodic rates of 122
μ
s to 500 ms, and end of
update cycle notification.
The RTC contains 256 bytes of battery-backed static RAM in two banks, namely, the standard bank and the
extended bank. The standard bank contains 10 bytes indicating time and date information, 4 bytes used as four
Control Register (A,B,C,D), and 114 bytes used as general purpose RAM. The extended bank has
128 bytes used as general purpose RAM.
Time, calendar, and alarm can be represented in either binary or BCD format. The format is determined by bit 2
of Control Register B. The hour is represented in 12 or 24 hour format and the format is selected by bit 1 of
Control Register B. Note that when changing the format, the time registers must be reinitialized to the
corresponding data format. See Control Register B in the following section for more information on the
configuration of the RTC functions.
The RTC module requires an external oscillating source of 32.768 KHz connected on the TRCX1 and RTCX2
pins. This clock signal is then divided down to 1 Hz signal. The divider chain is controlled by bits [6:4] of Control
Register A. Bits [3:0] of the Control Register A select one of the 15 taps from the divider chain to be used as a
periodic interrupt. See Control Register A in the following section for divider configuration and rate selections.
8.9.1.
RTC REGISTERS AND RAM
The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and
extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with
four registers, A–D, that are used for configuration of the RTC. The extended bank contains a full
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PDF描述 |
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| FW82801E | Intel 82801E Communications I/O Controller Hub (C-ICH) |
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| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
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