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參數(shù)資料
| 型號： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁數(shù)： | 198/284頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
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82371AB (PIIX4)
E
198
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to PIIX4 (read). It is used
by PIIX4 to signal when it is ready to transfer data and to add wait states to the current transaction. The DIOR#
signal is redefined as STROBE for transferring data from PIIX4 to the IDE device (write). It is the data strobe
signal driven by PIIX4 on which data is transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to PIIX4 (read). It is the
data strobe signal driven by the IDE device on which data is transferred during each rising and falling edge
transition. The IORDY signal is redefined as DMARDY# for transferring data from PIIX4 to the IDE device
(write). It is used by the IDE device to signal when it is ready to transfer data and to add wait states to the
current transaction.
All other signals on the IDE connector retain their functional definitions during Ultra DMA/33 operation.
Operation
Initial setup programming consists of enabling and performing the proper configuration of PIIX4 and the IDE
device for Ultra DMA/33 operation. For PIIX4, this consists of enabling Synchronous DMA mode and setting up
appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is followed. Once
programmed, the drive and PIIX4 control the transfer of data via the Ultra DMA/33 protocol. The actual data
transfer consists of three phases, a startup phase, a data transfer phase, and a burst termination phase.
The IDE device begins the startup phase by asserting DMARQ signal. When ready to begin the transfer, PIIX4
asserts DMACK# signal. When DMACK# signal is asserted, the host controller drives CS0# and CS1# inactive,
DA0–DA2 low, and the IDE device drives IOCS16# inactive. For write cycles, PIIX4 negates STOP, waits for the
IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, PIIX4
tri-states the DD lines, negates STOP, and asserts DMARDY#. The IDE device then sends the first data word
and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (PIIX4 writes, IDE device reads)
providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of
STROBE. The transmitter can pause the burst by holding STROBE high or low, resuming the burst by again
toggling STROBE. The receiver can pause the burst by negating DMARDY# and resumes the transfers by
asserting DMARDY#. PIIX4 pauses a burst transaction to prevent an internal line buffer over or under flow
condition, resuming once the condition has cleared. It may also pause a transaction if the current PRD byte
count has expired, resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst termination consists of a Stop
Request, Stop Acknowledge and transfer of CRC data. A Burst must first be paused as described above before
it can be terminated. PIIX4 can then stop the burst by asserting STOP, with the IDE device acknowledging by
negating DMARQ. The IDE device can then stop the burst by negating DMARQ and PIIX4 acknowledges by
asserting STOP. The transmitter then drives the STROBE signal to a high level. PIIX4 then drives the CRC
value onto the DD lines and negate DMACK#. The IDE device latches the CRC value on rising edge of
DMACK#. PIIX4 terminates a burst transfer if it needs to service the opposite IDE channel, if a Programmed I/O
(PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the
final PRD.
CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra DMA/33 transfers. The CRC value is
calculated for all data by both PIIX4 and the IDE device over the duration of the Ultra DMA/33 burst transfer
segment. This segment is defined as all data transferred with a valid STROBE edge from DDACK# assertion to
DDACK# negation. At the end of the transfer burst segment, PIIX4 drives the CRC value onto the DD[15:0]
signals. It is then latched by the IDE device on negation of DDACK#. The IDE device compares the PIIX4 CRC
value to its own and reports an error if their is a mismatch.
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| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
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