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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 73/180頁(yè) |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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6.0 Control Register Definitions–Function 1
Fusion 878A
6.3 Local Registers (Memory Mapped)
PCI Video Decoder
6-10
Conexant
100600B
0x100—Interrupt Status Register (INT_STAT)
This register provides the status of pending interrupt conditions. To clear the interrupts, read this register, then
write the same data back. A 1 in the write data clears the particular register bit. The interrupt /status bits can be
polled at any time.
Bits
Type
Default
Name
Description
[31:28]
RO
—
RISCS
Set when RISC status set bits are set in the RISC instruction. Reset when RISC
status reset bits are set. Status only, no interrupt.
[27]
RO
—
RISC_EN
A value of 0 indicates the DMA controller is currently disabled. Status only, no
interrupt.
[26]
RO
——
Reserved
[25]
RO
——
Reserved
[24]
RO
——
Reserved
[23:20]
RO
0000
—
Reserved
[19]
RR
0
SCERR
Set when the DMA EOL sync counter overflows. This is a severe error which
requires the software to restart the field capture process. Also set when SYNC
codes do not match in the data/instruction streams.
[18]
RR
0
OCERR
Set when the DMA controller detects a reserved/unused opcode in the
instruction sequence, or reserved/unused sync status in a SYNC instruction. In
general, this includes any detected RISC instruction error.
[17]
RR
0
PABORT
Set whenever the initiator receives a MASTER or TARGET ABORT.
[16]
RR
0
RIPERR
Set when a data parity error is detected (Parity Error Response must be set)
while the initiator is reading RISC instructions. RISC_ENABLE is reset by the
target to stop the DMA immediately.
[15]
RR
0
PPERR
Set when a parity error is detected on the PCI bus for any of the transactions,
R/W, address/data phases, initiator/target, or issued/sampled PERR, regardless
of the Parity Error Response bit. All parity errors are serious except for data
written to display.
[14]
RR
0
FDSR
Set when FIFO Data Stream Resynchronization occurs. The number of pixels,
lines, or modes passing through FIFO does not match RISC program
expectations.
[13]
RR
0
FTRGT
Set when a pixel data FIFO overrun condition results in the master, terminating
the transaction due to excessive target latency.
[12]
RR
0
FBUS
Set when a pixel data FIFO overrun condition is being handled by dropping as
many DWORDs as needed, indicating bus access latencies are long.
[11]
RR
0
RISCI
Set when the IRQ bit in the RISC instruction is set.
[10]
RO
0
Reserved
[9]
RO
0
Reserved
[8]
RO
0
Reserved
[7:6]
RO
0
Reserved
[5]
RO
0
Reserved
[4]
RO
0
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FVXO-HC53BR-FREQ | VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT |
| FVXO-HC72BR-FREQ | VCXO, CLOCK, 0.75 MHz - 180 MHz, HCMOS OUTPUT |
| FVXO-HC73B-FREQ | VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT |
| FVXO-LC52BR-FREQ | VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT |
| FVXO-LC72BR-FREQ | VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FUSZ03 | 制造商:Honeywell Sensing and Control 功能描述: |
| FUTURE 1AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2C PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 3D PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
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