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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 12/180頁(yè) |
| 文件大小： | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
3.0 Electrical Interfaces
PCI Video Decoder
3.5 I2C Serial EEPROM Interface
100600B
Conexant
3-25
3.5.2.3 Programming
and Write-Protect
The EEPROM can be programmed before soldering onto the PCB, or it may be
programmed through Fusion 878A using the I2C hardware or software modes.
The write transaction sequence is:
1.
START
2.
0xA0
3.
8-bit byte address
4.
8-bit write data
5.
STOP
This 3-byte transaction then initiates a programming cycle internal to the
EEPROM. The write completion status can be monitored by initiating another
write transaction and checking the ACK status. Anytime a transaction has been
aborted with a slave NACK, that implies the EEPROM device is still busy with
the internally timed programming cycle.
The upper half of a 24C02 device can be write-protected by adding a pull-up
resistor to the EEPROM WP pin. Just pull the pin to GND during programming.
3.5.3 Vital Product Data
Fusion 878A complies with the Vital Product Data (VPD) capability structure as
defined in the PCI Local Bus Specification Revision 2.2. The flag bit in the VPD
Capability register indicates the transfer of data between the VPD Data register
and the EEPROM.
To read information from the EEPROM, write a 0 to the VPD flag at the same
time you supply the 15-bit address to the VPD address bits of the VPD Capability
register. The Fusion 878A then sets the VPD flag after it completes reading 4
bytes from the EEPROM, returning Address +3, ... Address +0 (little endian
format). Software should monitor the flag to determine the correct time to read
the VPD Data Register.
To write information to the R/W portion of the EEPROM, write four bytes (a
DWORD) to the VPD Data Register, then set the flat bit to 1 while also supplying
the 15-bit address to the appropriate bits in the VPD Capability register. After
four bytes are written to the EEPROM, the Fusion 878A resets the flag bit to 0.
The VPD Data Register is byte-accessible; however, all data transfers between
the EEPROM and the Fusion 878A are 4-byte transactions.
3.5.3.1 Vital Product
Data EEPROM
Addressing
The 15-bit logical byte address maps to the EEPROM physical storage space
beginning at 0xFB. Only eight bits of the address field are supported. The
EEPROM physical address equals the (VPD logical address + 4) xor 0xFF. Since
all VPD accesses are a full DWORD, the four bytes will use the VPD address + 3
as its base. Decreasing the VPD logical address will then correspond to increasing
the EEPROM physical address.
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