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參數(shù)資料
| 型號： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 63/180頁 |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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100600B
Conexant
6-1
6
6.0 Control Register Definitions–Function 1
This chapter defines Function 1 address spaces. As in the previous chapter, the configuration address space
includes the pre-defined PCI configuration registers. The memory address space includes all the local registers
used by Fusion 878A to control the remaining portions of the device. Both the PCI configuration address space
and the memory address space start at memory location 0x00. The PCI-based system distinguishes the two
address spaces based on the Initialization Device Select, PCI address, and command signals that are issued
during the appropriate software commands.
6.1 PCI Configuration Space
The PCI configuration space defines the registers used to interface between the host and the PCI local bus.
Function 1 responds as a multimedia device. Each function has its own address space. AD[10:8] indicates which
function the PCI bus is addressing. AD[10:8] = 001 specifies Function 1. The register definitions in this chapter
apply only to Function 1.
The configuration space registers are described in the previous chapter. For a discussion on configuration
cycle addressing, refer to Section 3.6.4.1 of the PCI Local Bus Specification, Revision 2.2.
The configuration space is accessible at all times even though it is not typically accessed during normal
operation. These registers are normally accessed by the Power On Self Test (POST) code and by the device
driver during initialization time. Software will, however, read the status register during normal operation when a
PCI bus error occurs and is detected by Fusion 878A.
The configuration space is accessed when the IDSEL pin is high, and AD[1:0] equals 00; otherwise, the
cycle is ignored. The configuration register addresses are each offset by 4, since AD[1:0] equals 00.
Fusion 878A supports burst R/W cycles. Write operations to reserved, unimplemented, or read-only
registers/bits complete normally with the data discarded. Read accesses to reserved or unimplemented
registers/bits return a data value equal to 0.
Internal addressing of Fusion 878A registers occurs via AD[7:2] and the byte enable bits of the PCI bus. The
8-bit byte address for each of the following register locations is {AD[7:2], 00}.
CardBus CIS Pointer registers are not implemented in the Fusion 878A. User-definable features, BIST,
Cache Line Size, and Expansion ROM Base Address register are also not supported.
This section defines the organization of the registers within the 64-byte predefined header portion of the
configuration space. Figure 6-1 shows the configuration space header. For details on the PCI bus, refer to the
PCI Local Bus Specification, Revision 2.2.
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