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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 5/180頁(yè) |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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3.0 Electrical Interfaces
Fusion 878A
3.3 General Purpose I/O Port
PCI Video Decoder
3-18
Conexant
100600B
3.3.7 Digital Video Input Mode
The GPIO port can be configured to accept general digital data streams. The parts
contain a TG_RAM-based state machine that isolates the digital video input
events from the internal decoder timing. This allows the digital video input H and
V events to synchronize the sequencer, and allows the programmable output
events to be positioned where needed to synchronize the decoder.
The digital input port provides flexibility for interfacing to various video
standards. Software for programming the parts is included in the development kit
for interfacing to the supported video standards. Table 3-5 provides the alternate
pin definitions when using the digital video-in mode. Additional digital interfaces
may be implemented by changing the TG_RAM contents. Contact your local
Conexant sales office for more information.
3.3.7.1 CCIR656
CCIR656 is a 27 MBps interface in the form of Cb, Y, Cr, Y, Cb, etc. In this
sequence, the word sequence Cb, Y, Cr, refers to co-sited and color-difference
samples, and the following word, Y, corresponds to the next luminance sample.
In this interface, two timing reference codes, SAV and EAV occur at the start
and end of active video, respectively. These 4-byte codes occur at the outside
boundaries of the active video. In the active video line, 720 pixels correspond to
1440 samples; 1448 bytes comprise a video data block (one line of video with
reference codes).
The full video line consists of 1716 bytes (in 525 line systems) and 1728 bytes
(in 625 line systems). The line breaks into two parts. The first part is blanking,
which consists of the front porch, HSYNC, back porch, and 276 bytes (288 in 635
line systems) from EAV through SAV. The leading edge of HSYNC occurs
32-bytes (24 in 625 line systems) after the start of the digital line. The field
interval is aligned to this leading edge of HSYNC.
Figure 3-12 illustrates a diagram of the interface. For a full reference on this
standard, please refer to the International Telecommunications Union (ITU)
specification, ITU-R-BT656. This can be obtained from the ITU Web Site at
http://www.itu.int/publications/.
Table 3-5. Pin Definition of GPIO Port When Using Digital Video-In Mode
GPIO
Signal
Description
Pin
Number
[23]
CLKx1
Output signals for synchronizing to input video.
56
[22]
FIELD
57
[21]
VACTIVE
58
[20]
VSYNC
59
[19]
HACTIVE
60
[18]
HSYNC
61
[17]
Composite ACTIVE
67
[16]
Composite SYNC
68
[20]
VSYNC/FIELD
Input signals for synchronizing to input video.
59
[18]
HSYNC
61
[7:0]
DATA
Cb0, Y0, Cr0, Y1 ... Video data input at GPCLK = CLK × 2 rate.
79–86
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相關(guān)代理商/技術(shù)參數(shù) |
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| FUTURE 2AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2C PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
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