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參數(shù)資料
| 型號： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 161/180頁 |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.18 Digital Audio Packetizer
100600B
Conexant
2-57
bytes. The data following one line of length ALP_LEN will begin the next line
(no data lost).
The ALP_LEN sequence is repeated AFP_LEN times. The last 36-bit word
written to the FIFO contains the VRO end-of-audio-field status code (DWORD
data portion = don’t care). This whole field sequence repeats until ACAP_EN is
reset low. The end of data capture will be synchronized with the VRO code
DWORD. FIFO_ENABLE should be set high during audio capture to enable the
FIFO. If FIFO_ENABLE is reset, capture is immediately (asynchronously)
stopped, and the capture state machine begins its sequence from the start of the
next frame (FM1...).
2.18.5 Digital Audio Input
The digital audio interface consists of three input pins: ADATA, ALRCK, and
ASCLK. This three-wire interface can be used to capture 16-bit I2S style digital
audio (DA_DPM = 0) or more generic non-continuous packet synchronized data
bytes (DA_DPM = 1). The PCI clock will be used to re-sample the asynchronous
clock ASCLK, since it is at a much higher rate. The ALRCK and ADATA signals
are sampled with respect to this re-synchronized clock. Refer to the
2.18.5.1 Digital Audio
Input Mode
The digital audio is a serial bit stream where the highest ASCLK allowed is
64 x 48 kHz = 3.072 MHz. ADATA must supply at least 16 bits per left and 16
bits per right audio sample. The framing ALRCK clock is a square wave usually
aligned with the start of each sample.
The universal interface can be configured by several register values. The bit
DA_SCE (0 = rising, 1 = falling) chooses the edge of ASCLK used to sample the
bit stream on ADATA. The bit DA_LRI (0 = left, 1 = right) is used to determine
the left/right sample synchronized with the rising edge of ALRCK. It is assumed
that the left sample will lead and be paired with the following right sample. Thus
DA_LRI can be used to indicate which ALRCK edge points to start of the sample
coincident pair. (If a particular format is R then L oriented, then this will reverse
the order of data presented to memory, i.e., the right sample will be at the lower
address.) The 5-bit value DA_LRD is used to delay from each ALRCK edge,
DA_LRD ASCLKs before transferring the left or right shift-register data to a
parallel register. The value DA_LRD indicates the number of ASCLKs following
the edge of ALRCK where the first bit of the 16-bit data (regardless of serial
transfer order) can be found. The bit DA_MLB (0 = MSB 1st, 1 = LSB 1st)
determines the order that the data comes in so that the 16-bit samples delivered to
the packetizer can be properly aligned. Figure 2-25 illustrates an example of
audio input timing
Figure 2-25. Audio Input Timing
ASCLK
ADATA
ALRCK
MSB
. . .
LSB
MSB
LSB
Left 16-Bit Sample
Right 16-Bit Sample
879A_029
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