- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67592 > FUSION878A (CONEXANT SYSTEMS) COLOR SIGNAL DECODER, PQFP128 PDF資料下載
參數(shù)資料
| 型號： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 147/180頁 |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁當前第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁
Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.12 DMA Controller
100600B
Conexant
2-45
queued DWORDs. The DMA controller will ignore the FIFO trigger point
because it needs to empty the FIFO immediately. Otherwise it may not have a
chance to empty the rest of the FIFOs before it has to relinquish the bus. This is
not a concern in the packed mode because all three FIFOs are treated as one large
FIFO.
When the PCI target detects a parity error while the PCI initiator is reading the
instruction data, the DMA controller immediately stops burst data writes and
RISC instruction reads. This condition also causes an interrupt.
2.12.6 FIFO Overrun Conditions
There are cases where the Fusion 878A PCI initiator cannot gain control of the
PCI bus, and the DMA controller is not able to execute the necessary WRITE
instructions. Instead of writing data to the bus, the DMA controller reads data out
of the FIFO and discards the data. To the FIFO, it appears as if the DMA
controller is outputting to the bus. This allows the FIFO overruns to be handled
gracefully, with minimal loss of data. The Fusion 878A is not required to abort a
whole scan during FIFO overruns. The DMA controller keeps track of the data to
the nearest byte, and is able to deliver the rest of the scan line in case the FIFO
overrun condition is cleared.
The Fusion 878A DMA controller normally monitors the FIFO Full (FFULL)
counters to determine how full the FIFOs are. However, before the DMA
controller begins a burst write operation to process a WRITE instruction, it is
desirable to have some headroom in the FIFO allowing for more data to enter
while the PCI initiator is waiting for the target to respond. Hence, the Fusion
878A monitors the FIFO Almost Full (FAFULL) counters. The difference
between FFULL and FAFULL provides the necessary headroom to handle target
latency.
Before the DMA controller executes the address phase of a PCI write
transaction to process a WRITE instruction, the FIFO count value must be below
the FAFULL level. At all other times, the FIFOs must be maintained below the
FFULL level. The FIFO counters for all three FIFOs are monitored for full/almost
full conditions in both planar and packed modes.
Once the DMA controller begins the PCI bus transaction, it has committed to
a target DMA start address. If the FIFO overflows while it is waiting for the target
to respond, the initiator must terminate the transaction just after the target
responds. This is because the DMA controller has to start discarding the FIFO
data, since the target pointer and the data are out of sync. This terminating
condition will be communicated to the Fusion 878A device driver by setting an
interrupt bit that indicates interfacing to unreasonably slow targets (FBUS).
If an instruction is exhausted while the FIFO is in an overrun condition, the
Fusion 878A DMA controller will continue discarding the FIFO data during the
next pre-fetched instruction as well. If the DMA controller runs out of RISC
instructions and the FIFO continues to fill up, then PCI bus access is still denied.
The DMA controller continues discarding FIFO data for the remainder of that
scan line. Once the Fusion 878A DMA controller detects the EOL control bits
from the FIFO, it will attempt to gain access to the PCI bus and resynchronize
itself with the RISC instruction EOL status bits. However, if the DMA controller
is not successful in getting control of the bus, it will keep track of the number of
scan lines discarded out of the FIFO and will resynchronize itself with the RISC
program based on the number of EOL control signals detected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FVXO-HC53BR-FREQ | VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT |
| FVXO-HC72BR-FREQ | VCXO, CLOCK, 0.75 MHz - 180 MHz, HCMOS OUTPUT |
| FVXO-HC73B-FREQ | VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT |
| FVXO-LC52BR-FREQ | VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT |
| FVXO-LC72BR-FREQ | VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FUSZ03 | 制造商:Honeywell Sensing and Control 功能描述: |
| FUTURE 1AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2C PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 3D PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。