參數(shù)資料
型號： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 50/51頁
文件大?。?/td> 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
8
Datasheet
Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2,
“Chip Enable Truth Table” on page 12) reduces decoder logic typically required for multi-chip
designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 1.
When the device is disabled (see Table 2 on page 12)and the RP# pinis at VCC, the standby mode
is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is required
from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL)
from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the
status register is cleared.
The Intel StrataFlash memory devices are available in several package types. The 64-Mbit is
available in 56-lead SSOP (Shrink Small Outline Package) and BGA* package (micro Ball Grid
Array). The 32-Mbit is available in 56-lead TSOP (Thin Small Outline Package) and 56-lead
SSOP. Figures 2, 3, and 4 show the pinouts.
Figure 1. Intel StrataFlash Memory Block Diagram
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Input Buffer
Ou
tp
u
t
Mult
iplexer
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Da
ta
Re
gi
s
te
r
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output Buffer
GND
V
CC
V
PEN
CE
0
CE
1
CE
2
WE#
OE#
RP#
BYTE#
Command
User
Interface
32-Mbit: A
0-A21
64-Mbit: A
0- A22
DQ
0 -DQ15
V
CC
W
ri
te
B
u
ffer
Write State
Machine
Multiplexer
Query
STS
V
CCQ
CE
Logic
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