參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 41/51頁
文件大小： 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
46
Datasheet
6.6
AC Characteristics— Write Operations(1,2)
NOTE: CEX low is defined as the first edge of CE0,CE1,or CE2 that enables the device. CEX high is defined at
thefirst edgeofCE0,CE1,orCE2 that disables the device (see Table2onpage12).
1. Read timingcharacteristics duringblock erase, program, and lock-bit configuration operations are the same
as duringread-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CEX or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going
high (whichever goes high first). Hence, tWP =tWLWH =tELEH =tWLEH =tELWH.IfCEX is driven low 10 ns
before WE# going low, WE# pulse width requirement decreases to tWP -10 ns.
5. Refer to Table4onpage17 for valid AIN and DIN for block erase, program, or lock-bit configuration.
6. Writepulse widthhigh(tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or
WE# going low (whichever goes low first). Hence, tWPH =tWHWL =tEHEL =tWHEL =tEHWL.
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. VPEN should be held at VPENH (and if necessary RP# should be held at VHH) until determination of block
erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
Versions
Valid for All
Speeds
#
Sym
Parameter
Notes
Min
Max
Unit
W1
tPHWL (tPHEL)
RP# High Recovery to WE# (CEX ) GoingLow
3
1
s
W2
tELWL (tWLEL)CEX (WE#) Low to WE# (CEX) GoingLow
4
0
ns
W3
tWP
Write Pulse Width
4
70
ns
W4
tDVWH (tDVEH)
Data Setup to WE# (CEX ) GoingHigh
5
50
ns
W5
tAVWH (tAVEH)
Address SetuptoWE# (CEX ) GoingHigh
5
50
ns
W6
tWHEH (tEHWH)CEX (WE#) Hold from WE# (CEX)High
10
ns
W7
tWHDX (tEHDX)
DataHoldfrom WE# (CEX )High
0
ns
W8
tWHAX (tEHAX)
Address Hold from WE# (CEX )High
0
ns
W9
tWPH
WritePulse WidthHigh
6
30
ns
W10
tPHHWH (tPHHEH)RP# VHH SetuptoWE# (CEX ) GoingHigh
3
0
ns
W11
tVPWH (tVPEH)VPEN SetuptoWE# (CEX ) GoingHigh
3
0
ns
W12
tWHGL (tEHGL)
Write Recovery before Read
7
35
ns
W13
tWHRL (tEHRL)WE# (CEX ) HightoSTS Going Low
8
90
ns
W14
tQVPH
RP# VHH Hold from Valid SRD, STS GoingHigh
3,8,9
0
ns
W15
tQVVL
VPEN Hold from Valid SRD, STS GoingHigh
3,8,9
0
ns
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