參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 38/51頁
文件大?。?/td> 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
Datasheet
43
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic "0." Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timingends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
NOTE: AC test inputs are driven at 2.7 V for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and output timing ends,
at 1.35 V (50% of VCCQ). Input rise and fall times (10% to 90%) <10 ns.
NOTE: CL Includes JigCapacitance
Figure 12. Transient Input/Output Reference Waveform for VCCQ =5.0 V± 10% (Standard
Testing Configuration)
Output
Test Points
Input
2.0
0.8
2.0
0.8
2.4
0.45
Figure 13. Transient Input/Output Reference Waveform
Output
Test Points
Input
1.35
2.7
0.0
1.35
Figure 14. Transient Equivelent Testing Load Circuit
Device
Under Test
Out
R
L =3.3 k
1N914
1.3V
C
L
Table 20. Test Configuration Capacitance Loading Value
Test Configuration
CL (pF)
VCCQ =5.0 V ± 10%
100
VCCQ =2.7 V3.6 V
50
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