參數(shù)資料
型號: E28F320J5-120
廠商: INTEL CORP
元件分類: PROM
英文描述: StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述: 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝: 14 X 20 MM, TSOP-56
文件頁數(shù): 43/51頁
文件大?。?/td> 651K
代理商: E28F320J5-120
28F320J5 and 28F640J5
48
Datasheet
0606_18
NOTE: STS is shown in its default mode (RY/BY#).
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
valid.
Figure 17. AC Waveform for Reset Operation
STS (R)
RP# (P)
V
IH
V
IL
V
IH
V
IL
P1
P2
Table 21. Reset Specifications(1)
#
Sym
Parameter
Notes
Min
Max
P1
tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable)
235
P2
tPHRH
RP#HightoReset during BlockErase,Program, or Lock-Bit
Configuration
3
100
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