參數(shù)資料
型號(hào): E28F320J5-120
廠商: INTEL CORP
元件分類(lèi): PROM
英文描述: StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述: 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝: 14 X 20 MM, TSOP-56
文件頁(yè)數(shù): 30/51頁(yè)
文件大?。?/td> 651K
代理商: E28F320J5-120
28F320J5 and 28F640J5
36
Datasheet
0606_11
Figure 10. Set Block Lock-Bit Flowchart
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Standby
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations
Write FFH after the last lock-bit set operation to place device in read
array mode.
Bus
Operation
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command, in cases where multiple lock-bits are set before full
status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
1
0
Standby
Command
Set Block/Master
Lock-Bit Setup
Set Block or Master
Lock-Bit Confirm
Comments
Data = 60H
Addr =Block Address (Block),
Device Address (Master)
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Check SR.7
1 = WSM Ready
0=WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect RP# = V
IH
(Set Master Lock-Bit Operation)
RP# = V
IH, Master Lock-Bit Is Set
(set Block Lock-Bit Operation)
Read Status Register
Data (See Above)
Voltage Range Error
Device Protect Error
SR.3 =
SR. 1 =
1
0
1
0
Command Sequence
Error
SR.4,5 =
1
0
Set Lock-Bit Error
SR.4 =
1
0
Read
Status Register Data
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.4
1 = Set Lock-Bit Error
Set Lock-Bit
Successful
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