參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 24/51頁
文件大小： 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
30
Datasheet
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of
250 ns.
Table 15. Write Protection Alternatives
Operation
Master
Lock-Bit
Block
Lock-Bit
RP#
Effect
Block Erase or Program
0
VIH or
VHH
Block Erase and Program Enabled
X1
VIH
Block is Locked. Block Erase and Program Disabled
VHH
Block Lock-Bit Override. Block Erase and Program
Enabled
Set or Clear Block Lock-Bits
0
X
VIH or
VHH
Set or Clear Block Lock-Bit Enabled
1X
VIH
Master Lock-Bit Is Set. Set or Clear Block Lock-Bit
Disabled
VHH
Master Lock-Bit Override. Set or Clear Block Lock-Bit
Enabled
Set Master Lock-Bit
X
VIH
Set Master Lock-Bit Disabled
VHH
Set Master Lock-Bit Enabled
Table 16. Configuration Coding Definitions
Reserved
Pulse on
Program
Complete(1)
Pulse on
Erase
Complete(1)
Bits 7—2
Bit 1
Bit 0
DQ7–DQ2 = Reserved
DQ1–DQ0 = STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse mode
such that the STS pin pulses low then high when the operation
indicated by the given configuration is completed.
Configuration Command Sequences for STS pin configuration
(maskingbits DQ7–DQ2 to 00h) are as follows:
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
DQ7–DQ2 are reserved for future use.
default (DQ1–DQ0 = 00) RY/BY#, level mode
— usedtocontrol HOLD toamemorycontroller toprevent
accessinga flash memory subsystem while any flash device's
WSM is busy.
configuration 01 ER INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has completed a Block Erase or sequence of
Queued Block Erases. Helpful for reformattingblocks after file
system free space reclamation or “cleanup”
configuration 10 PR INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has complete a Program operation. Provides
highest performance for servicing continuous buffer write
operations.
configuration 11 ER/PR INT, pulse mode
— used to generate system interrupts to trigger servicing of
flash arrays when either erase or program operations are
completed when a common interrupt service routine is desired.
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