參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁(yè)數(shù)： 22/51頁(yè)
文件大?。?/td> 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
Datasheet
29
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared. The CUI will remain in read status register mode
until a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations occur only when VCC and VPEN are valid. With
VPEN ≤ VPENLK, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master
lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH,SR.1
and SR.4 will be set to “1” and the operation will fail. Set block lock-bit operations while VIH <
RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit
operation requires that RP# = VHH. If it is attempted with RP# = VIH,SR.1and SR.4 will be setto
“1” and the operation will fail. Set master lock-bit operations with VIH <RP# < VHH produce
spurious results and should not be attempted.
4.12
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the
master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits
command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-
Bits command and VHH on the RP# pin. This command is invalid while the WSM is running or the
device is suspended. See Table 14, “Identifier Codes” on page 25 for a summary of hardware and
software write protection options.
Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup
is first written. The device automatically outputs status register data when read (see Figure 11,
“Clear Block Lock-Bit Flowchart” on page 37). The CPU can detect completion of the clear block
lock-bits event by analyzing the STS pin output or status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can
only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while
VPEN ≤ VPENLK, SR.3 and SR.5 will be set to “1.” A successful clear block lock-bits operation
requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH.If itis
attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to “1” and the
operation will fail. A clear block lock-bits operation with VIH <RP# < VHH produce spurious
results and should not be attempted.
If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range or
RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear
block lock-bits is required to initialize block lock-bit contents to known values. Once the master
lock-bit is set, it cannot be cleared.
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