參數(shù)資料
型號： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 25/51頁
文件大小： 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
Datasheet
31
Table 17. Status Register Definition
WSMS
ESS
ECLBS
PSLBS
VPENS
R
DPS
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HighZWhen
Busy?
Status Register Bits
Notes
No
Yes
Yes
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
1 = Error in Programming or Set Master/Block
Lock-Bit
0 = Successful Programming or Set Master/Block
Lock Bit
SR.3 = PROGRAMMING VOLTAGE STATUS
1 = Low Programming Voltage Detected,
Operation Aborted
0 = Programming VoltageOK
SR.2 = RESERVED FOR FUTURE ENHANCEMENTS
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
Detected, Operation Abort
0= Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Check STS or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–SR.0 are not driven while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
SR.3 does not provide a continuous
programming voltage level indication. The
WSM interrogates and indicates the
programming voltage level only after Block
Erase, Program, Set Block/Master Lock-Bit, or
Clear Block Lock-Bits command sequences.
SR.1 does not provide a continuous indication
of master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit,
and RP# only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, dependingon the
attempted operation, if the block lock-bit is set,
master lock-bit is set, and/or RP# is not VHH.
Read the block lock and master lock
configuration codes using the Read Identifier
Codes command to determine master and
block lock-bit status.
SR.2 and SR.0 are reserved for future use
and should be masked when pollingthe status
register.
Table 18. eXtended Status Register Definition
WBS
Reserved
bit 7
bits 6—0
HighZWhen
Busy?
Status Register Bits
Notes
No
Yes
XSR.7 = WRITE BUFFER STATUS
1 = Write buffer available
0 = Write buffer not available
XSR.6–XSR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
After a Buffer-Write command, XSR.7 = 1
indicates that a Write Buffer is available.
SR.6–SR.0 are reserved for future use and
shouldbemasked whenpollingthestatus
register.
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