參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁(yè)數(shù)： 18/51頁(yè)
文件大?。?/td> 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
Datasheet
25
NOTES:
1. A0 is not used in either x8 or x16 modes when obtainingthe identifier codes. The lowest order address line is
A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h).
2. X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory
map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration
is complete and whether the operation completed successfully. It may be read at any time by
writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until another valid command is written. The status
register contents are latched on the falling edge of OE# or the first edge of CE0,CE1,or CE2 that
enables the device (see Table 2). OE# must toggle to VIH or the device must be disabled (Table 2)
before further reads to update the status register latch. The Read Status Register command
functions independently of the VPEN voltage.RP# canbe VIH or VHH.
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the WSM completes or suspends the operation. Device I/O pins DQ0–DQ6 and DQ8–DQ15
are placed in a high-impedance state. When the operation completes or suspends (check status
register bit 7), all contents of the status register are valid when read.
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits indicate various failure conditions (see Table 16).
By allowing system software to reset these bits, several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in sequence) may be performed. The status register
may be polled to determine if an error occurred during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions
independently of the applied VPEN voltage. RP# can be VIH or VHH. The Clear Status Register
command is only valid when the WSM is off or the device is suspended.
Table 14. Identifier Codes
Code
Address(1)
Data
Manufacture Code
00000
(00) 89
Device Code
32-Mbit
00001
(00) 14
64-Mbit
00001
(00) 15
Block Lock Configuration
X
0002(2)
BlockIsUnlocked
DQ0 =0
BlockIsLocked
DQ0 =1
Reserved for Future Use
DQ1–7
Master Lock Configuration
00003
Device Is Unlocked
DQ0 =0
Device Is Locked
DQ0 =1
Reserved for Future Use
DQ1–7
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