參數(shù)資料
型號(hào)： E28F320J5-120
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
中文描述： 2M X 16 FLASH 5V PROM, 150 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁數(shù)： 39/51頁
文件大?。?/td> 651K
代理商： E28F320J5-120
28F320J5 and 28F640J5
44
Datasheet
6.5
AC Characteristics—Read-Only Operations(1)
NOTE: CEX low is defined as the first edge of CE0,CE1,or CE2 that enables the device. CEX high is defined at
thefirst edgeofCE0,CE1,orCE2 that disables the device (seeTable 2).
1. See Figure 15, “AC Waveform for Read Operations” on page 45 for the maximum allowable input slew rate.
2. See Figure 12, Figure 13,and Figure14onpag e43, for testingcharacteristics
3. OE#may be delayeduptotELQV-tGLQV after the first edge of CE0,CE1,or CE2 that enables the device (see
Table 2) without impact on tELQV.
Versions
5 V ± 10% VCCQ
–120/–150(2)
(All units in ns unless otherwise noted)
2.7 V—10% VCCQ
–120/–150(2)
#
Sym
Parameter
Notes
Min
Max
R1
tAVAV
Read/Write Cycle Time
32 Mbit
120
130 at +85° C
64 Mbit
150
R2
tAVQV
Address to Output Delay
32 Mbit
120
130 at +85° C
64 Mbit
150
R3
tELQV
CEX to Output Delay
32 Mbit
3
120
130 at +85° C
64 Mbit
3
150
R4
tGLQV
OE# to Output Delay
3
50
R5
tPHQV
RP#HightoOutputDelay
32 Mbit
180
64 Mbit
210
R6
tELQX
CEX to Output in Low Z
4
0
R7
tGLQX
OE# to Output in Low Z
4
0
R8
tEHQZ
CEX HightoOutputinHighZ
4
55
R9
tGHQZ
OE#HightoOutputinHighZ
4
15
R10
tOH
Output Hold from Address, CEX, or OE# Change,
Whichever Occurs First
40
R11
tELFL
tELFH
CEX Low to BYTE# High or Low
4
10
R12
tFLQV
tFHQV
BYTE# to Output Delay
1000
R13
tFLQZ
BYTE# to Output in High Z
4
1000
R14
tEHEL
CEx Disable Pulse Width
4
10
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