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參數資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數： | 8/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 8 of 43
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
LVTTL Output
Transmit Clock Output
. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs have
no fixed phase relationship to REFCLKx±.
Receive Path Data and Status Signals
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
LVTTL Output,
synchronous to the
selected RXCLK±
output or REFCLKx±
input
Parallel Data Output
. RXDx[7:0] parallel data outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are complementary clocks
operating at the character rate. The RXDx[7:0] outputs for the associated receive
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half-rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXDx[7:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
LVTTL Output,
synchronous to the
selected RXCLK±
output or REFCLKx±
input
Parallel Status Output
. RXSTA[2:0] status outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are complementary clocks
operating at the character rate. The RXSTAx[2:0] outputs for the associated receive
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half-rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXSTAx[2:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.
When the decoder is bypassed, RXSTx[1:0] become the two low-order bits of the 10-
bit received character. RXSTx[2] = HIGH indicates the presence of a Comma
character in the Output Register. When the decoder is enabled, RXSTx[2:0] provide
status of the received signal. See
Table 11
for a list of received character status.
Receive Path Clock Signals
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
LVTTL Output Clock
Receive Clock Output
. RXCLKx± is the receive interface clock used to control timing
of the RXDx[7:0] and RXSTA[2:0] parallel outputs. The source of the RXCLKx±
outputs is selected by the RXCKSELx latch via the device configuration interface.
These true and complement clocks are used to control timing of data output transfers.
These clocks are output continuously at either the dual-character rate (1/20
th
the
serial bit-rate) or character rate (1/10
th
the serial bit-rate) of the data being received,
as selected by RXRATEx. When configured such that the output data path is clocked
by the REFCLKx± instead of a recovered clock, the RXCLKx± output drivers present
a buffered or divided form (depending on RXRATEx) of the associated REFCLKx±
that are delayed in phase to align with the data. This phase difference allows the user
to select the optimal clock (REFCLKx± or RXCLK±) for setup/hold timing for their
specific system.
When REFCLKx± is a full-rate clock, the RXCLKx± rate depends on the value of
RXRATEx.
When REFCLKx± is a half-rate clock and RXCKSELx = 0, the RXCLKx± rate depends
on the value of RXRATEx.
When REFCLKx± is a half-rate clock and RXCKSELx=1, the RXCLKx± rate does not
depend on the value of RXRATEx and operates at the same rate as REFCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset
. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. See
Table 9
for the initialize values of
the device configuration latches.
Pin Descriptions
(continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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