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| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 14/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 14 of 43
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for transmission lines. These drivers accept data from the
Transmit Shifters. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines. When
configured for local loopback (LPENx = HIGH), all enabled
serial drivers are configured to drive a static differential logic
1. To achieve OBSAI RP3 compliancy, the serial output drivers
must be AC-coupled to the transmission medium.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note
. When a disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
data on the serial outputs may not meet all timing specifi-
cations for up to 250
μ
s
the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
CYP(V)(W)15G0403DXB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VI
DIFF
> 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC-
restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
The local internal loopback (LPENx) allows the serial transmit
data outputs to be routed internally back to the Clock and Data
Recovery circuit associated with each channel. When
configured for local loopback, the associated transmit serial
driver outputs are forced to output a differential logic-1. This
prevents local diagnostic patterns from being broadcast to
attached remote receivers.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
analog amplitude above amplitude level selected by
SDASELx
transition density above the specified limit
range controls report the received data stream inside
normal frequency range (±1500 ppm
[30]
)
receive channel enabled
Presence of reference clock
ULCx is not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the selected
receive interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELx latch via device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in
Table 5
. This control
input affects the analog monitors for all receive channels.
The Analog Signal Detect monitors are active for the Line
Receiver as selected by the associated INSELx input. When
configured for local loopback, no input receivers are selected,
and the LFIx output for each channel reports only the receive
VCO frequency out-of-range and transition density status of
the associated transmit signal. When local loopback is active,
the associated Analog Signal Detect Monitor is disabled.
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
when the incoming data stream resumes after a time in
which it has been “missing.”
when the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the REFCLKx±
Table 5. Analog Amplitude Detect Valid Signal Levels
[8]
SDASEL
00
01
10
11
Typical Signal with Peak Amplitudes Above
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Note:
8.
The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
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