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參數資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數： | 11/43頁 |
| 文件大小： | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 11 of 43
CYP(V)(W)15G0403DXB HOTLink II Operation
The CYP(V)(W)15G0403DXB is a highly configurable,
independent clocking, quad-channel transceiver designed to
support reliable transfer of large quantities of data, using high-
speed serial links from multiple sources to multiple destina-
tions. This device supports four single-byte channels.
CYP(V)(W)15G0403DXB Transmit Data Path
Input Register
The bits in the Input Register for each channel support
different assignments, based on if the input data is encoded or
unencoded. These assignments are shown in
Table 1
.
When the ENCODER is enabled, each input register captures
eight data bits and two control bits on each input clock cycle.
When the Encoder is bypassed, the control bits are part of the
pre-encoded 10-bit character.
When the Encoder is enabled, the TXCTx[1:0] bits are inter-
preted along with the associated TXDx[7:0] character to
generate a specific 10-bit transmission character.
Phase-Align Buffer
Data from each Input Register is passed to the associated
Phase-Align Buffer, when the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using TXCLKx| (TXCKSELx = 0 and
TXRATEx = 0). When the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using REFCLKx± (TXCKSELx = 1) and
REFCLKx± is a full-rate clock, the associated Phase
Alignment Buffer in the transmit path is bypassed. These
buffers are used to absorb clock phase differences between
the TXCLKx input clock and the internal character clock for
that channel.
Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond
the handling capacity of the Phase Align Buffer, TXERRx is
Analog I/O
OUTA1±
OUTB1±
OUTC1±
OUTD1±
CML Differential
Output
Primary Differential Serial Data Output
. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
CML Differential
Output
Secondary Differential Serial Data Output
. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-
optic transmitter modules, and must be AC-coupled for PECL-compatible connections.
INA1±
INB1±
INC1±
IND1±
Differential Input
Primary Differential Serial Data Input
. The INx1± input accepts the serial data
stream for deserialization and decoding. The INx1± serial stream is passed to the
receive CDR circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
Differential Input
Secondary Differential Serial Data Input
. The INx2± input accepts the serial data
stream for deserialization and decoding. The INx2± serial stream is passed to the
receiver CDR circuit to extract the data content when INSELx = LOW.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained
high for
≥
5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock
.
TDO
3-State LVTTL
Output
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not selected.
TDI
LVTTL Input,
internal pull-up
Test Data In
. JTAG data input port.
TRST
LVTTL Input,
internal pull-up
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V
CC
GND
+3.3V Power
.
Signal and Power Ground for all internal circuits
.
Pin Descriptions
(continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYRF69103 | Programmable Radio on Chip Low Power |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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