參數(shù)資料
型號： CYP15G0403DXB
廠商： Cypress Semiconductor Corp.
英文描述： Independent Clock Quad HOTLink II Transceiver(獨(dú)立時鐘，四熱連接II收發(fā)器)
中文描述： 獨(dú)立時鐘四路HOTLink II收發(fā)器（獨(dú)立時鐘，四熱連接二收發(fā)器）
文件頁數(shù)： 25/43頁
文件大?。?/td> 744K
代理商： CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 25 of 43
Maximum Ratings
Above which the useful life may be impaired. User guidelines
only, not tested
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State.......................................–0.5V to V
CC
+ 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V
CC
+ 0.5V
Static Discharge Voltage..........................................> 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Power-up Requirements
The CYP(V)(W)15G0403DXB requires one power-supply. The
Voltage on any input or I/O pin cannot exceed the power pin
during power-up.
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
+3.3V ±5%
+3.3V ±5%
CYP(V)(W)15G0403DXB DC Electrical Characteristics
Parameter
LVTTL-compatible Outputs
V
OHT
Output HIGH Voltage
V
OLT
Output LOW Voltage
I
OST
Output Short Circuit Current
I
OZL
High-Z Output Leakage Current
LVTTL-compatible Inputs
V
IHT
Input HIGH Voltage
V
ILT
Input LOW Voltage
I
IHT
Input HIGH Current
Description
Test Conditions
Min.
Max.
Unit
I
OH
=
4 mA, V
CC
= Min.
I
OL
= 4 mA, V
CC
= Min.
V
OUT
= 0V
[10]
, V
CC
= 3.3V
V
OUT
= 0V, V
CC
2.4
V
V
0.4
–100
20
–20
–20
mA
μA
2.0
–0.5
V
CC
+ 0.3
0.8
1.5
+40
–1.5
–40
+200
–200
V
V
REFCLKx Input, V
IN
= V
CC
Other Inputs, V
IN
= V
CC
REFCLKx Input, V
IN
= 0.0V
Other Inputs, V
IN
= 0.0V
V
IN
= V
CC
V
IN
= 0.0V
mA
μA
mA
μA
μA
μA
I
ILT
Input LOW Current
I
IHPDT
I
ILPUT
LVDIFF Inputs: REFCLKx
±
V
DIFF[11]
Input Differential Voltage
V
IHHP
Highest Input HIGH Voltage
V
ILLP
Lowest Input LOW voltage
V
COMREF[12]
Common Mode Range
3-Level Inputs
V
IHH
Three-Level Input HIGH Voltage
V
IMM
Three-Level Input MID Voltage
V
ILL
Three-Level Input LOW Voltage
I
IHH
Input HIGH Current
I
IMM
Input MID current
I
ILL
Input LOW current
Differential CML Serial Outputs: OUTA1
±
, OUTA2
±
, OUTB1
±
, OUTB2
±,
OUTC1
±
, OUTC2
±
, OUTD1
±
, OUTD2
±
V
OHC
Output HIGH Voltage
(V
cc
Referenced)
Input HIGH Current with internal pull-down
Input LOW Current with internal pull-up
400
1.2
0.0
1.0
V
CC
V
CC
V
CC
/2
V
CC
– 1.2V
mV
V
V
V
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
0.87 * V
CC
0.47 * V
CC
0.0
V
CC
V
V
V
μA
μA
μA
0.53 * V
CC
0.13 * V
CC
200
50
–200
–50
100
differential load
150
differential load
V
CC
– 0.5
V
CC
– 0.5
V
CC
– 0.2
V
CC
– 0.2
V
V
Notes:
10. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
11.
This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when
the true (+) input is more positive than the complement (
) input. A logic-0 exists when the complement (
) input is more positive than true (+) input.
12. The common mode range defines the allowable range of REFCLKx+ and REFCLKx
when REFCLKx+ = REFCLKx
. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
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