- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYP15G0403DXB (Cypress Semiconductor Corp.) Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨(dú)立時(shí)鐘四路HOTLink II收發(fā)器（獨(dú)立時(shí)鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 19/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 19 of 43
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[7:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Table 9. Device Configuration and Control Latch Descriptions
Name
RFMODEA[1:0]
RFMODEB[1:0]
RFMODEC[1:0]
RFMODED[1:0]
Signal Description
Reframe Mode Select
. The initialization value of the RFMODEx [1:0] latches = 10. RFMODEx is used to
select the operating mode of the framer. When RFMODEx[1:0] = 00, the low-latency framer is selected. This
frames on each occurrence of the selected framing character(s) in the received data stream. This mode of
framing stretches the recovered clock for one or multiple cycles to align that clock with the recovered data.
When RFMODEx[1:0] = 01, the alternate mode Multi-Byte parallel framer is selected. This requires detection
of the selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four
directly adjacent characters. The recovered character clock remains in the same phasing regardless of
character offset. When RFMODEx[1:0] =10, the Cypress-mode Multi-Byte parallel framer is selected. This
requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits,
before the character boundaries are adjusted. The recovered character clock remains in the same phasing
regardless of character offset. RFMODEx[1:0] = 11 is reserved for test.
Framing Character Select
. The initialization value of the FRAMCHARx latch = 1. FRAMCHARx is used to
select the character or portion of a character used for framing of each channel’s received data stream. When
FRAMCHARx = 1, the framer looks for either disparity of the K28.5 character. When FRAMCHARx = 0, the
framer looks for either disparity of the 8-bit Comma characters. The specific bit combinations of these framing
characters are listed in
Table 6
.
Receiver Decoder Mode Select
. The initialization value of the DECMODEx latch = 1. DECMODEx selects
the Decoder Mode used for the associated channel. When DECMODEx = 1 and decoder is enabled, the
Cypress Decoding Mode is used. When DECMODEx = 0 and decoder is enabled, the Alternate Decoding
mode is used. When the decoder is enabled (DECBYPx = 1), the 10-bit transmission characters are decoded
using
Table 15
and
Table 16
. The column used in the Special Characters
Table 16
is determined by the
DECMODEx latch.
Receiver Decoder Bypass
. The initialization value of the DECBYPx latch = 1. DECBYPx selects if the
Receiver Decoder is enabled or bypassed. When DECBYPx = 1, the decoder is enabled and the Decoder
Mode is selected by DECMODEx. When DECBYPx = 0, the decoder is bypassed and raw 10-bit characters
are passed through the receiver.
Receive Clock Select
. The initialization value of the RXCKSELx latch = 1.
RXCKSELx selects the receive
clock source used to transfer data to the Output Registers and the clock source for the RXCLK
±
output. When
RXCKSELx = 1, the associated Output Registers
,
are clocked by REFCLKx± at the associated RXCLKx
±
output buffer. When RXCKSELx = 0, the associated Output Registers, are clocked by the Recovered Byte
clock at the associated RXCLKx
±
output buffer. These output clocks may operate at the character-rate or half
the character-rate as selected by RXRATEx.
Receive Clock Rate Select
. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select
the rate of the RXCLKx± clock output.
When RXRATEx = 1 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at half the character rate. Data for the associated receive channels should be
latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at the character rate. Data for the associated receive channels should be latched
on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at half the character rate. Data for the
associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at the character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXCKSELx = 1 and REFCLKx± is a half-rate clock, the value of RXRATEx is not interpreted and the
RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half the
character rate. Data for the associated receive channels should be latched alternately on the rising edge of
RXCLKx+ and RXCLKx–.
FRAMCHARA
FRAMCHARB
FRAMCHARC
FRAMCHARD
DECMODEA
DECMODEB
DECMODEC
DECMODED
DECBYPA
DECBYPB
DECBYPC
DECBYPD
RXCKSELA
RXCKSELB
RXCKSELC
RXCKSELD
RXRATEA
RXRATEB
RXRATEC
RXRATED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYRF69103 | Programmable Radio on Chip Low Power |
| CYRF69213 | Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | Programmable Radio on Chip Low Power |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。