參數(shù)資料
型號(hào)： CYP15G0403DXB
廠商： Cypress Semiconductor Corp.
英文描述： Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
中文描述： 獨(dú)立時(shí)鐘四路HOTLink II收發(fā)器（獨(dú)立時(shí)鐘，四熱連接二收發(fā)器）
文件頁(yè)數(shù)： 21/43頁(yè)
文件大?。?/td> 744K
代理商： CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 21 of 43
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets all four channels.
2. Set the static receiver latch bank for the target channel. May
be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
3. Set the static transmitter latch bank for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional step if the default settings match
the desired configuration.]
4. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and transmit channels. May be
performed using a global operation, if the application
permits it. [Required step.]
5. Reset the Phase Alignment Buffer for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional if phase align buffer is
bypassed.]
When a receive channel is configured with the decoder
bypassed and the receive clock selected as recovered clock
in half-rate mode (DECBYPx = 0, RXRATEx = 1, RXCKSELx
= 0), the channel cannot be dynamically reconfigured to
enable the decoder with RXCLKx selected as the REFCLKx
(DECBYPx = 1, RXCKSELx = 1). If such a change is desired,
a global reset should be performed and all channels should be
reconfigured to the desired settings.
OE1A
OE1B
OE1C
OE1D
Primary Differential Serial Data Output Driver Enable
. The initialization value of the OE1x latch = 0. OE1x
selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1, the associated
serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0,
the associated serial data output driver is disabled. When a driver is disabled via the configuration interface,
it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled
state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled
LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal clock
domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the
initialization of the Phase Alignment Buffer.
Global Enable
. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx
= 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable
. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal
ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel,
FGLEN forces the global update of the target latch banks.
PABRSTA
PABRSTB
PABRSTC
PABRSTD
GLEN[11..0]
FGLEN[2..0]
Table 9. Device Configuration and Control Latch Descriptions
(continued)
Name
Signal Description
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